109 lines
4.7 KiB
Text
109 lines
4.7 KiB
Text
.In
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.nr H1 1
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.NH
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CLOSE-UP LOOK
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.NH 2
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What is EM?
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.PP
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As the abstract of the IR-81 rapport on EM
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.[ [
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description of a machine architecture
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.]]
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says: \*(OQEM is a family
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of intermediate languages designed for producing portable compilers.\*(CQ
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Because EM is to be used on a wide range of languages and processors,
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the instruction set is kept simple enough to allow easy translation to,
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or interpretation on, almost any processor. Yet it is also powerful enough
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to accommodate easy translation from almost any block-structured language.
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.PP
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Even though EM was designed in the early 1980s, it
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is based on
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.\" already shows strong signs of being influenced by
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the (then innovative) RISC architecture. All instructions
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have 0 or 1 operands, there are no fancy addressing modes as in the
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68020's\*(Si move.w a3(_array,d3.w*2), -(sp)\*(So, no explicit registers,
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although instructions for higher languages
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such as array-operations, multiway branches (case) and
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floating point operations are provided.
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.PP
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To fully understand the discussion in the following chapters,
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the reader should at least have some knowledge of EM.
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.NH 2
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What is SPARC?
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.PP
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According to Sun's RISC tutorial: \*(OQSun Microsystems has designed a RISC
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architecture, called SPARC, and has implemented that architecture with
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the Sun-4 family of supercomputing workstations and servers. SPARC stands
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for Scalable Processor ARChitecture, emphasizing its applicability to
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large as well as small machines.\*(CQ
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.PP
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In sharp contrast to EM, SPARC does have
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explicit registers (31 integer and 32 floating point, all of which
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are 32 bits wide) and
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does not support any high level language operations: it does not even have
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multiplication or division instructions. Because the SPARC design is
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very straightforward, all instructions could be hard-coded (no microcode
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involved) to
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provided extremely high performance. All register-to-register operations
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require exactly one clock cycle, and all register-to-memory and
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memory-to-register operations require two clock cycles, one to retrieve
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the instruction and one to access external memory. At a clock speed of
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over 20 MHz this means that well over 10 VAX MIPS can be achieved:
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more than 4 times the speed of a 15 MHz 68020 used in the Sun3/50.
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.PP
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As above, the reader should also have some general knowledge about
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the SPARC processer to be able to understand the following chapters.
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.NH 2
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What exactly is a (fast) backend?
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.PP
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To put in the simplest of ways: a (fast) backend is a set of routines to
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translate EM code to code that will run 'on the metal' (for example the SPARC
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processor). The distinction between full-fledged backends (code generators)
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.[ [
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The table driven code generator
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.]]
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and fast backends (code expanders)
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.[ [
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The Code Expander Generator
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.]]
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is related to
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the compilation-time vs. run-time trade off. Code generators generate
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efficient code and code expanders generate code very efficient.
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For details about code expanders see also
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.[ [
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The design of very fast portable compilers
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.]].
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.PP
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The reasons for us to implement a code expander are numerous: Our first reason to
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implement a code expander, rather than a code generator was that implementing a
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code expander would be hard enough already. Code generators only give
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more problems and there were already enough problems to be solved. Secondly,
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we knew we would never be able to compete with original SPARC compilers due
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to loss of information in the frontends (see also chapter 5). By implementing
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a code expander we might be able to outrun the existing compilers on a
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completely different terrain: compile speed.
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.PP
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The third 'reason' to implement a code expander lies a little deeper and was
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not discovered until we had actually started the implementation... It was only
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then that we found out that for certain architectures, such as the SPARC,
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the idea behind the code-expander is not necessarily inferior to that
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behind a code-generator. It seems that for highly orthogonal instruction
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sets it is possible to generate near optimal code without using the
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code-expander. We have to say, however, that this is only true for our
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optimized version of the code-expander. With the original code-expander
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it would not have been possible to generate near-optimal code for the
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SPARC processor.
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.NH 2
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So, what are the main differences between EM and SPARC?
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.PP
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The main
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difference between EM and SPARC is the stack versus register orientation.
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The other differences, such as the presence of high level language
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operations in EM, can easily be overcome by subroutines,
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or small pieces of in-line SPARC code.
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The design-part of this project mostly concentrates on
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building a bridge between EM's stack and SPARC's registers.
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.PP
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In the next chapter we will make a list of all our design problems which
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will then be discussed in chapter 4.
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.bp
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