728 lines
19 KiB
Text
728 lines
19 KiB
Text
REGISTERS
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/* Registers are allocated top down. The odd order below is to make sure
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* that cheap registers get allocated first.
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*
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* Attributes may have at most one of: int, float, long, double. These
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* indicate that the register is used to store a value of that type. If
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* your register can store more than one type, create an alias. Registers
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* with none of these cannot be copied by the code generator (and so cannot
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* be moved from register to register or spilt).
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*/
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r4 int volatile;
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r5 int volatile;
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r6 int volatile;
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r7 int volatile;
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r8 int volatile;
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r9 int volatile;
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r10 int volatile;
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r11 int volatile;
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r12 int volatile;
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r13 int volatile;
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r14 int volatile;
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r15 int volatile;
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r24 int volatile;
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r25 int volatile;
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r2 int volatile iret;
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r3 int volatile;
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r17 named("r16") int;
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r18 named("r18") int;
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r19 named("r19") int;
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r20 named("r20") int;
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r21 named("r21") int;
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r22 named("r22") int;
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r23 named("r23") int;
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r4r5 named("r4", "r5") aliases(r4, r5) long volatile;
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r6r7 named("r6", "r7") aliases(r6, r7) long volatile;
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r8r9 named("r8", "r9") aliases(r8, r9) long volatile;
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r10r11 named("r10", "r11") aliases(r10, r11) long volatile;
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r12r13 named("r12", "r13") aliases(r12, r13) long volatile;
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r14r15 named("r14", "r15") aliases(r14, r15) long volatile;
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r24r25 named("r24", "r25") aliases(r24, r25) long volatile;
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r2r3 named("r2", "r3") aliases(r2, r3) long volatile lret;
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f0 float volatile fret;
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f1 float volatile;
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f2 float volatile;
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f3 float volatile;
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f4 float volatile;
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f5 float volatile;
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f6 float volatile;
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f7 float volatile;
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f8 float volatile;
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f9 float volatile;
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f10 float volatile;
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f11 float volatile;
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f12 float volatile;
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f13 float volatile;
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f14 float volatile;
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f15 float volatile;
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f16 float volatile;
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f17 float volatile;
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f18 float volatile;
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f19 float volatile;
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f20 float;
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f21 float;
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f22 float;
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f23 float;
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f24 float;
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f25 float;
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f26 float;
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f27 float;
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f28 float;
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f29 float;
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f30 float;
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/* f31 is used by the compiler as a temporary. */
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d0 named("f0") aliases(f0) double volatile dret;
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d1 named("f1") aliases(f1) double volatile;
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d2 named("f2") aliases(f2) double volatile;
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d3 named("f3") aliases(f3) double volatile;
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d4 named("f4") aliases(f4) double volatile;
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d5 named("f5") aliases(f5) double volatile;
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d6 named("f6") aliases(f6) double volatile;
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d7 named("f7") aliases(f7) double volatile;
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d8 named("f8") aliases(f8) double volatile;
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d9 named("f9") aliases(f9) double volatile;
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d10 named("f10") aliases(f10) double volatile;
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d11 named("f11") aliases(f11) double volatile;
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d12 named("f12") aliases(f12) double volatile;
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d13 named("f13") aliases(f13) double volatile;
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d14 named("f14") aliases(f14) double volatile;
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d15 named("f15") aliases(f15) double volatile;
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d16 named("f16") aliases(f16) double volatile;
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d17 named("f17") aliases(f17) double volatile;
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d18 named("f18") aliases(f18) double volatile;
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d19 named("f19") aliases(f19) double volatile;
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d20 named("f20") aliases(f20) double;
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d21 named("f21") aliases(f21) double;
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d22 named("f22") aliases(f22) double;
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d23 named("f23") aliases(f23) double;
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d24 named("f24") aliases(f24) double;
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d25 named("f25") aliases(f25) double;
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d26 named("f26") aliases(f26) double;
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d27 named("f27") aliases(f27) double;
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d28 named("f28") aliases(f28) double;
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d29 named("f29") aliases(f29) double;
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d30 named("f30") aliases(f30) double;
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DECLARATIONS
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ubyteX; /* bottom 8 bits valid, the rest undefined */
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ubyte0; /* bottom 8 bits valid, the rest 0 */
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ushortX; /* bottom 16 bits valid, the rest undefined */
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ushort0; /* bottom 16 bits valid, the rest 0 */
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address fragment;
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PATTERNS
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/* Special */
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PAIR(BLOCK.I, BLOCK.I);
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/* Miscellaneous special things */
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PUSH.I(in:(int)reg)
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emit "addiu sp, sp, -4"
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emit "sw %in, 0(sp)"
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cost 8;
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PUSH.L(in:(long)reg)
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emit "addiu sp, sp, -8"
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emit "sw %in.0, 0(sp)"
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emit "sw %in.1, 4(sp)"
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cost 12;
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PUSH.F(in:(float)reg)
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emit "addiu sp, sp, -4"
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emit "swc1 %in, 0(sp)"
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cost 8;
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PUSH.D(in:(double)reg)
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emit "addiu sp, sp, -8"
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emit "sdc1 %in, 0(sp)"
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cost 8;
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out:(int)reg = POP.I
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emit "lw %out, 0(sp)"
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emit "addiu sp, sp, 4"
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cost 8;
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out:(long)reg = POP.L
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emit "lw %out.0, 4(sp)"
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emit "lw %out.1, 0(sp)"
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emit "addiu sp, sp, 8"
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cost 12;
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out:(float)reg = POP.F
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emit "lwc1 %out, 0(sp)"
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emit "addiu sp, sp, 4"
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cost 8;
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out:(double)reg = POP.D
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emit "ldc1 %out, 0(sp)"
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emit "addiu sp, sp, 8"
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cost 8;
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SETRET.I(in:(iret)reg)
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emit "! setret.i"
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cost 1;
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SETRET.L(in:(lret)reg)
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emit "! setret.l"
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cost 1;
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SETRET.F(in:(fret)reg)
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emit "! setret.f"
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cost 1;
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SETRET.D(in:(dret)reg)
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emit "! setret.d"
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cost 1;
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STACKADJUST.I(delta:CONST.I)
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when signed_constant(%delta, 16)
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emit "addiu sp, sp, $delta"
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cost 4;
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STACKADJUST.I(in:(int)reg)
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emit "addu sp, sp, %in"
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cost 4;
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STACKADJUST.I(NEG.I(in:(int)reg))
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emit "subu sp, sp, %in"
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cost 4;
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out:(int)reg = GETFP.I
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emit "mov %out, fp"
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cost 4;
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SETFP.I(in:(int)reg)
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emit "mov fp, %in"
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cost 4;
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out:(int)reg = CHAINFP.I(in:(int)reg)
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emit "lw %out, 0(%in)"
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cost 4;
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out:(int)reg = FPTOAB.I(GETFP.I)
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emit "addiu %out, fp, 8"
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cost 4;
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out:(int)reg = FPTOAB.I(in:(int)reg)
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emit "addiu %out, %in, 8"
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cost 4;
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out:(int)reg = FPTOLB.I(in:(int)reg)
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with %out == %in
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cost 1;
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out:(int)reg = GETSP.I
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emit "mov %out, sp"
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cost 4;
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SETSP.I(in:(int)reg)
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emit "mov sp, %in"
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cost 4;
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out:(int)reg = ANY.I
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cost 1;
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out:(long)reg = ANY.L
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cost 1;
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/* Memory operations */
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/* Stores */
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STORE.L(addr:address, value:(long)reg)
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emit "sw %value.0, 4+%addr"
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emit "sw %value.1, 0+%addr"
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cost 8;
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STORE.I(addr:address, value:(int)reg)
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emit "sw %value, %addr"
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cost 4;
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STOREH.I(addr:address, value:(int)ushortX)
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emit "sh %value, %addr"
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cost 4;
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STOREB.I(addr:address, value:(int)ubyteX)
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emit "sb %value, %addr"
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cost 4;
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STORE.F(addr:address, value:(float)reg)
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emit "swc1 %value, %addr"
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cost 4;
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STORE.D(addr:address, value:(double)reg)
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emit "sdc1 %value, %addr"
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cost 4;
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/* Loads */
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out:(int)reg = LOAD.I(addr:address)
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emit "lw %out, %addr"
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cost 4;
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/* We can't just load directly because %out.0 and %addr might share
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* a register, resulting in %addr being corrupted before %out.1 is
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* loaded. */
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out:(long)reg = LOAD.L(addr:address)
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emit "lw at, 4+%addr"
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emit "lw %out.1, 0+%addr"
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emit "mov %out.0, at"
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cost 12;
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out:(int)ushort0 = LOADH.I(addr:address)
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emit "lh %out, %addr"
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cost 4;
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out:(int)ubyte0 = LOADB.I(addr:address)
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emit "lb %out, %addr"
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cost 4;
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out:(float)reg = LOAD.F(addr:address)
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emit "lwc1 %out, %addr"
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cost 4;
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out:(double)reg = LOAD.D(addr:address)
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emit "ldc1 %out, %addr"
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cost 4;
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/* ubyte intrinsics */
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out:(int)ubyteX = in:(int)ubyte0
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with %out == %in
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emit "! ubyte0 -> ubyteX"
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cost 1;
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out:(int)ubyte0 = in:(int)ubyteX
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emit "andiu %out, %in, 0xff ! ubyteX -> ubyte0"
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cost 4;
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out:(int)reg = in:(int)ubyte0
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with %out == %in
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emit "! ubyte0 -> reg"
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cost 4;
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out:(int)ubyteX = in:(int)reg
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with %out == %in
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emit "! reg -> ubyteX"
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cost 1;
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/* ushort intrinsics */
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out:(int)ushortX = in:(int)ushort0
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with %out == %in
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emit "! ushort0 -> ushortX"
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cost 1;
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out:(int)ushort0 = in:(int)ushortX
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emit "andiu %out, %in, 0xffff ! ushortX -> ushort0"
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cost 4;
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out:(int)reg = in:(int)ushort0
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with %out == %in
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emit "! ushort0 -> reg"
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cost 4;
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out:(int)ushortX = in:(int)reg
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with %out == %in
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emit "! reg -> ushortX"
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cost 1;
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/* Extensions and conversions */
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out:(int)reg = EXTENDB.I(in:(int)reg)
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emit "seb %out, %in"
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cost 4;
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out:(int)reg = EXTENDH.I(in:(int)reg)
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emit "seh %out, %in"
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cost 4;
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out:(int)reg = FROMSI.I(in:(int)reg)
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with %out == %in
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emit "! FROMSI.I(int) -> int"
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cost 1;
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out:(int)reg = FROMUI.I(in:(int)reg)
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with %out == %in
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emit "! FROMUI.I(int) -> int"
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cost 1;
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out:(long)reg = FROMSI.L(in:(int)reg)
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emit "mov %out.0, %in"
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emit "sra %out.1, %in, 31"
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cost 8;
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out:(long)reg = FROMUI.L(in:(int)reg)
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emit "mr %out.0, %in"
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emit "li %out.1, 0"
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cost 8;
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out:(lret)reg = FROMIPAIR.L(in1:(int)reg, in2:(int)reg)
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emit "mov %out.0, %in1"
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emit "mov %out.1, %in2"
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cost 8;
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out:(int)reg = FROML0.I(in:(long)reg)
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emit "mov %out, %in.0"
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cost 4;
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out:(int)reg = FROML1.I(in:(long)reg)
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emit "mov %out, %in.1"
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cost 4;
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/* Locals */
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out:(int)reg = in:LOCAL.I
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emit "addiu %out, fp, $in"
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cost 4;
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address = in:LOCAL.I
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emit "$in(fp)";
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/* Memory addressing modes */
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address = ADD.I(addr:(int)reg, offset:CONST.I)
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when signed_constant(%offset, 16)
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emit "$offset(%addr)";
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address = addr:(int)reg
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emit "0(%addr)";
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/* Branches */
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JUMP(addr:BLOCK.I)
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emit "b $addr"
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emit "nop"
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cost 8;
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FARJUMP(addr:LABEL.I)
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with corrupted(volatile)
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emit "b $addr"
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emit "nop"
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cost 8;
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JUMP(dest:(int)reg)
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emit "jr %dest"
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emit "nop"
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cost 8;
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CJUMPEQ(COMPARESI.I(left:(int)reg, right:(int)reg), PAIR(true:BLOCK.I, false:BLOCK.I))
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emit "beq %left, %right, $true"
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emit "nop"
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emit "b $false"
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emit "nop"
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cost 16;
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CJUMPLT(COMPARESI.I(left:(int)reg, right:(int)reg), PAIR(true:BLOCK.I, false:BLOCK.I))
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emit "slt at, %left, %right"
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emit "bne at, zero, $true"
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emit "nop"
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emit "b $false"
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emit "nop"
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cost 20;
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CJUMPLT(COMPAREUI.I(left:(int)reg, right:(int)reg), PAIR(true:BLOCK.I, false:BLOCK.I))
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emit "sltu at, %left, %right"
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emit "bne at, zero, $true"
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emit "nop"
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emit "b $false"
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emit "nop"
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cost 20;
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CJUMPLT(COMPARESI.I(left:(int)reg, right:CONST.I), PAIR(true:BLOCK.I, false:BLOCK.I))
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when specific_constant(%right, 0)
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emit "bltz %left, $true"
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emit "nop"
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emit "b $false"
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emit "nop"
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cost 16;
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CJUMPLE(COMPARESI.I(left:(int)reg, right:(int)reg), PAIR(true:BLOCK.I, false:BLOCK.I))
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emit "sle at, %left, %right"
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emit "bne at, zero, $true"
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emit "nop"
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emit "b $false"
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emit "nop"
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cost 20;
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CJUMPLE(COMPAREUI.I(left:(int)reg, right:(int)reg), PAIR(true:BLOCK.I, false:BLOCK.I))
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emit "sleu at, %left, %right"
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emit "bne at, zero, $true"
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emit "nop"
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emit "b $false"
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emit "nop"
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cost 20;
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CJUMPLE(COMPARESI.I(left:(int)reg, right:CONST.I), PAIR(true:BLOCK.I, false:BLOCK.I))
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when specific_constant(%right, 0)
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emit "blez %left, $true"
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emit "nop"
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emit "b $false"
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emit "nop"
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cost 16;
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COMPAREUI.I(left:(int)reg, right:(int)reg);
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#define CALLLABEL(insn) \
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insn (dest:LABEL.I) \
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with corrupted(volatile) \
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emit "bal $dest" \
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emit "nop" \
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cost 8;
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CALLLABEL(CALL)
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out:(iret)reg = CALLLABEL(CALL.I)
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out:(lret)reg = CALLLABEL(CALL.L)
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#define CALLINDIRECT(insn) \
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insn (dest:(int)reg) \
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with corrupted(volatile) \
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emit "jalr %dest" \
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emit "nop" \
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cost 8;
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CALLINDIRECT(CALL)
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out:(iret)reg = CALLINDIRECT(CALL.I)
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out:(lret)reg = CALLINDIRECT(CALL.L)
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JUMP(dest:LABEL.I)
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emit "b $dest"
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emit "nop"
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cost 8;
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/* Comparisons */
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/* The COMPARE nodes return tristate integer values; -1, 0 or 1. */
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out:(int)reg = COMPARESI.I(left:(int)reg, right:(int)reg)
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emit "slt at, %left, %right"
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emit "bne at, zero, 1f"
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emit "li %out, -1" /* delay slot */
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emit "slt %out, %right, %left"
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emit "1:"
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cost 20;
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out:(int)reg = COMPAREUI.I(left:(int)reg, right:(int)reg)
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emit "sltu at, %left, %right"
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emit "bne at, zero, 1f"
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emit "li %out, -1" /* delay slot */
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emit "sltu %out, %right, %left"
|
|
emit "1:"
|
|
cost 20;
|
|
|
|
out:(int)reg = COMPARED.I(left:(double)reg, right:(double)reg)
|
|
emit "c.lt.d 0, %left, %right"
|
|
emit "bc1t 0, 1f"
|
|
emit "li %out, -1" /* delay slot */
|
|
emit "c.lt.d 0, %right, %left"
|
|
emit "li %out, 1"
|
|
emit "movf %out, zero, 0"
|
|
cost 28;
|
|
|
|
/* Booleans */
|
|
|
|
/* If 0 then 1, else 0 */
|
|
out:(int)reg = IFEQ.I(in:(int)reg)
|
|
emit "sleu %out, %in, zero"
|
|
cost 4;
|
|
|
|
/* If -1 then 1, else 0 */
|
|
out:(int)reg = IFLT.I(in:(int)reg)
|
|
emit "slt %out, %in, zero"
|
|
cost 4;
|
|
|
|
/* If 1 or 0 then 1, else 0 */
|
|
out:(int)reg = IFLE.I(in:(int)reg)
|
|
emit "sle %out, %in, zero"
|
|
cost 4;
|
|
|
|
|
|
|
|
/* Conversions */
|
|
|
|
#if 0
|
|
out:(int)reg = CIU44(in:(int)reg)
|
|
with %out == %in
|
|
emit "! ciu44"
|
|
cost 4;
|
|
|
|
out:(int)reg = CUI44(in:(int)reg)
|
|
with %out == %in
|
|
emit "! cui44"
|
|
cost 4;
|
|
#endif
|
|
|
|
/* ALU operations */
|
|
|
|
/* reg + reg */
|
|
#define ALUR(name, instr) \
|
|
out:(int)reg = name(left:(int)reg, right:(int)reg) \
|
|
emit instr " %out, %left, %right" \
|
|
cost 4; \
|
|
|
|
/* reg + const */
|
|
#define ALUC(name, instr) \
|
|
out:(int)reg = name(left:(int)reg, right:CONST.I) \
|
|
when signed_constant(%right, 16) \
|
|
emit instr " %out, %left, $right" \
|
|
cost 4; \
|
|
|
|
/* const + reg */
|
|
#define ALUC_reversed(name, instr) \
|
|
out:(int)reg = name(left:CONST.I, right:(int)reg) \
|
|
when signed_constant(%left, 16) \
|
|
emit instr " %out, %right, $left" \
|
|
cost 4; \
|
|
|
|
/* reg + const AND const + reg */
|
|
#define ALUCC(name, instr) \
|
|
ALUC(name, instr) \
|
|
ALUC_reversed(name, instr)
|
|
|
|
ALUR(ADD.I, "addu")
|
|
ALUCC(ADD.I, "addiu")
|
|
|
|
out:(int)reg = SUB.I(left:(int)reg, right:(int)reg)
|
|
emit "subu %out, %right, %left"
|
|
cost 4;
|
|
|
|
out:(int)reg = SUB.I(left:(int)reg, right:CONST.I)
|
|
emit "addiu %out, %left, -[$right]"
|
|
cost 4;
|
|
|
|
out:(int)reg = MOD.I(left:(int)reg, right:(int)reg)
|
|
emit "div %left, %right"
|
|
emit "mfhi %out"
|
|
cost 8;
|
|
|
|
out:(int)reg = MODU.I(left:(int)reg, right:(int)reg)
|
|
emit "divu %left, %right"
|
|
emit "mfhi %out"
|
|
cost 8;
|
|
|
|
ALUR(MUL.I, "mul")
|
|
|
|
ALUR(DIV.I, "divw")
|
|
ALUR(DIVU.I, "divwu")
|
|
|
|
ALUR(ASL.I, "sllv")
|
|
ALUC(ASL.I, "sll")
|
|
ALUR(ASR.I, "srav")
|
|
ALUC(ASR.I, "sra")
|
|
|
|
ALUR(LSL.I, "sllv")
|
|
ALUC(LSL.I, "sll")
|
|
ALUR(LSR.I, "srlv")
|
|
ALUC(LSR.I, "srl")
|
|
|
|
out:(int)reg = NEG.I(left:(int)reg)
|
|
emit "neg %out, %left"
|
|
cost 4;
|
|
|
|
out:(int)reg = NOT.I(in:(int)reg)
|
|
emit "nor %out, %in, %in"
|
|
cost 4;
|
|
|
|
ALUR(AND.I, "and")
|
|
ALUCC(AND.I, "andi.")
|
|
|
|
ALUR(OR.I, "or")
|
|
ALUCC(OR.I, "ori")
|
|
|
|
ALUR(EOR.I, "xor")
|
|
ALUCC(EOR.I, "xori")
|
|
|
|
out:(int)reg = value:LABEL.I
|
|
emit "la %out, $value"
|
|
cost 4;
|
|
|
|
out:(int)reg = value:BLOCK.I
|
|
emit "la %out, $value"
|
|
cost 4;
|
|
|
|
out:(int)reg = value:CONST.I
|
|
emit "li %out, $value"
|
|
cost 4;
|
|
|
|
|
|
|
|
/* FPU operations */
|
|
|
|
/* Doubles */
|
|
|
|
out:(double)reg = ADDF.D(left:(double)reg, right:(double)reg)
|
|
emit "add.d %out, %left, %right"
|
|
cost 4;
|
|
|
|
out:(double)reg = SUBF.D(left:(double)reg, right:(double)reg)
|
|
emit "sub.d %out, %left, %right"
|
|
cost 4;
|
|
|
|
out:(double)reg = MULF.D(left:(double)reg, right:(double)reg)
|
|
emit "mul.d %out, %left, %right"
|
|
cost 4;
|
|
|
|
out:(double)reg = DIVF.D(left:(double)reg, right:(double)reg)
|
|
emit "div.d %out, %left, %right"
|
|
cost 4;
|
|
|
|
out:(double)reg = FROMSI.D(in:(int)reg)
|
|
emit "mtc1 %out, %in"
|
|
emit "cvt.d.w %out, %out"
|
|
cost 4;
|
|
|
|
/* Floats */
|
|
|
|
out:(float)reg = ADDF.F(left:(float)reg, right:(float)reg)
|
|
emit "add.d %out, %left, %right"
|
|
cost 4;
|
|
|
|
out:(float)reg = SUBF.F(left:(float)reg, right:(float)reg)
|
|
emit "sub.d %out, %left, %right"
|
|
cost 4;
|
|
|
|
out:(float)reg = MULF.F(left:(float)reg, right:(float)reg)
|
|
emit "mul.d %out, %left, %right"
|
|
cost 4;
|
|
|
|
out:(float)reg = DIVF.F(left:(float)reg, right:(float)reg)
|
|
emit "div.d %out, %left, %right"
|
|
cost 4;
|
|
|
|
out:(float)reg = FROMSI.F(in:(int)reg)
|
|
emit "mtc1 %out, %in"
|
|
emit "cvt.s.w %out, %out"
|
|
cost 4;
|
|
|
|
/* vim: set sw=4 ts=4 expandtab : */
|
|
|