From 215bc1aab4faa62699ad3f069fc215dc3c46a77e Mon Sep 17 00:00:00 2001
From: Michael Matz <matz@suse.de>
Date: Mon, 15 Jul 2019 19:34:08 +0200
Subject: [PATCH] riscv: Add sar, shr insn

fixes 92_enum_bitfield.
---
 riscv64-gen.c | 8 ++++++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/riscv64-gen.c b/riscv64-gen.c
index e395582b..3c7109d6 100644
--- a/riscv64-gen.c
+++ b/riscv64-gen.c
@@ -621,8 +621,6 @@ static void gen_opil(int op, int ll)
     d = ireg(d);
     switch (op) {
     case '%':
-    case TOK_SAR:
-    case TOK_SHR:
     case TOK_PDIV:
     default:
         tcc_error("implement me: %s(%s)", __FUNCTION__, get_tok_str(op, NULL));
@@ -633,6 +631,12 @@ static void gen_opil(int op, int ll)
     case '-':
         o(0x33 | (d << 7) | (a << 15) | (b << 20) | (0x20 << 25)); //sub d, a, b
         break;
+    case TOK_SAR:
+        o(0x33 | (d << 7) | (a << 15) | (b << 20) | (5 << 12) | (1 << 30)); //sra d, a, b
+        break;
+    case TOK_SHR:
+        o(0x33 | (d << 7) | (a << 15) | (b << 20) | (5 << 12)); //srl d, a, b
+        break;
     case TOK_SHL:
         o(0x33 | (d << 7) | (a << 15) | (b << 20) | (1 << 12)); //sll d, a, b
         break;