From 5dc241fee11691fc168477261a92e99b7c0b7873 Mon Sep 17 00:00:00 2001
From: noneofyourbusiness <noneofyourbusiness@danwin1210.de>
Date: Sun, 10 Dec 2023 15:22:41 +0100
Subject: [PATCH] riscv64-tok.h: add Zicsr pseudoinstructions, registers

---
 riscv64-tok.h | 23 +++++++++++++++++++++++
 1 file changed, 23 insertions(+)

diff --git a/riscv64-tok.h b/riscv64-tok.h
index c8a6e8e3..92369d92 100644
--- a/riscv64-tok.h
+++ b/riscv64-tok.h
@@ -340,6 +340,29 @@
  DEF_ASM(csrrwi)
  DEF_ASM(csrrsi)
  DEF_ASM(csrrci)
+ /* registers */
+ DEF_ASM(cycle)
+ DEF_ASM(fcsr)
+ DEF_ASM(fflags)
+ DEF_ASM(frm)
+ DEF_ASM(instret)
+ DEF_ASM(time)
+ /* RV32I-only */
+ DEF_ASM(cycleh)
+ DEF_ASM(instreth)
+ DEF_ASM(timeh)
+ /* pseudo */
+ DEF_ASM(csrc)
+ DEF_ASM(csrci)
+ DEF_ASM(csrr)
+ DEF_ASM(csrs)
+ DEF_ASM(csrsi)
+ DEF_ASM(csrw)
+ DEF_ASM(csrwi)
+ DEF_ASM(frcsr)
+ DEF_ASM(frrm)
+ DEF_ASM(fscsr)
+ DEF_ASM(fsrm)
 
 /* Privileged Instructions */