From fb1fb8219ccf4813d63edf8c40fddc756e0c60cc Mon Sep 17 00:00:00 2001 From: Michael Matz Date: Thu, 16 Apr 2020 00:00:13 +0200 Subject: [PATCH] riscv64: fcvt.d.s doesn't need a rounding mode it doesn't round so the RM field can be zero. According to some sourcs it should be set to zero by software in these cases, and the binutils disassembler doesn't like us setting it to 7. This shouldn't matter in practice, but who knows. --- riscv64-gen.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/riscv64-gen.c b/riscv64-gen.c index 47961b3a..a0584fb3 100644 --- a/riscv64-gen.c +++ b/riscv64-gen.c @@ -1176,9 +1176,9 @@ ST_FUNC void gen_cvt_ftof(int dt) rs = gv(RC_FLOAT); rd = get_reg(RC_FLOAT); if (dt == VT_DOUBLE) - EI(0x53, 7, freg(rd), freg(rs), 0x21 << 5); // fcvt.d.s RD, RS (dyn rm) + EI(0x53, 0, freg(rd), freg(rs), 0x21 << 5); // fcvt.d.s RD, RS (no rm) else - EI(0x53, 7, freg(rd), freg(rs), (0x20 << 5) | 1); // fcvt.s.d RD, RS + EI(0x53, 7, freg(rd), freg(rs), (0x20 << 5) | 1); // fcvt.s.d RD, RS (dyn rm) vtop->r = rd; } }