100 lines
5.3 KiB
Org Mode
100 lines
5.3 KiB
Org Mode
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#+title: 65∞2 Instruction Set Architecture
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#+author: d0p1
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** Registers
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- PC :: Program counter (32bit)
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- AC :: Accumulator (32bit)
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- X :: X register (32bit)
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- Y :: Y register (32bit)
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- SR :: status register (32bit)
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- SP :: stack pointer (32bit)
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Status register flags
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#+begin_src
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31 0
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+------ .... ----+-+-+-+-+-+-+-+-+
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| |N|V| |B|D|I|Z|C|
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+------ .... ----+-+-+-+-+-+-+-+-+
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#+end_src
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- N :: Negative
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The negative flag (N) indicates the presence of a set sign bit in bit-position 31.
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- V :: Overflow
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The overflow flag (V) indicates overflow with signed binary arithmetics.
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- B :: Break
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- D :: Decimal
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- I :: Interrupt
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- Z :: Zero
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The zero flag (Z) indicates a value of all zero bits.
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- C :: Carry
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** Addressing Modes
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*** Implied Addressing
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*** Immediate Addressing
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A size and a literal operand is given immediately after the instruction.
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#+begin_src asm
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LDA.B #7
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LDA.W #300
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LDA.D #$DEADBEEF
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#+end_src
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*** Absolute Addressing
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** Opcodes
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#+begin_src
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+----+----------+-----------+-------+----+-----------+-----------+-----------+----+----------+-----------+----------+----+-----------+-----------+-----------+----+
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| | -0 | -1 | -2 | -3 | -4 | -5 | -6 | -7 | -8 | -9 | -A | -B | -C | -D | -E | -F |
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+----+----------+-----------+-------+----+-----------+-----------+-----------+----+----------+-----------+----------+----+-----------+-----------+-----------+----+
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| 0- | BRK impl | ORA X,ind | | | | ORA zpg | ASL zpg | | PHP impl | ORA # | ASL A | | | ORA abs | ASL abs | |
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| 1- | BPL rel | ORA ind,Y | | | | ORA zpg,X | ASL zpg,X | | CLC impl | ORA abs,Y | | | | ORA abs,X | ASL abs,X | |
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| 2- | JSR abs | AND X,ind | | | BIT zpg | AND zpg | ROL zpg | | PLP impl | AND # | ROL A | | BIT abs | AND abs | ROL abs | |
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| 3- | BMI rel | AND ind,Y | | | | AND zpg,X | ROL zpg,X | | SEC impl | AND abs,Y | | | | AND abs,X | ROL abs,X | |
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| 4- | RTI impl | EOR X,ind | | | | EOR zpg | LSR zpg | | PHA impl | EOR # | LSR A | | JMP abs | EOR abs | LSR abs | |
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| 5- | BVC rel | EOR ind,Y | | | | EOR zpg,X | LSR zpg,X | | CLI impl | EOR abs,Y | | | | EOR abs,X | LSR abs,X | |
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| 6- | RTS impl | ADC X,ind | | | | ADC zpg | ROR zpg | | PLA impl | ADC # | ROR A | | JMP ind | ADC abs | ROR abs | |
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| 7- | BVS rel | ADC ind,Y | | | | ADC zpg,X | ROR zpg,X | | SEI impl | ADC abs,Y | | | | ADC abs,X | ROR abs,X | |
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| 8- | | STA X,ind | | | STY zpg | STA zpg | STX zpg | | DEY impl | | TXA impl | | STY abs | STA abs | STX abs | |
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| 9- | BCC rel | STA ind,Y | | | STY zpg,X | STA zpg,X | STX zpg,Y | | TYA impl | STA abs,Y | TXS impl | | | STA abs,X | | |
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| A- | LDY # | LDA X,ind | LDX # | | LDY zpg | LDA zpg | LDX zpg | | TAY impl | LDA # | TAX impl | | LDY abs | LDA abs | LDX abs | |
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| B- | BCS rel | LDA ind,Y | | | LDY zpg,X | LDA zpg,X | LDX zpg,Y | | CLV impl | LDA abs,Y | TSX impl | | LDY abs,X | LDA abs,X | LDX abs,Y | |
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| C- | CPY # | CMP X,ind | | | CPY zpg | CMP zpg | DEC zpg | | INY impl | CMP # | DEX impl | | CPY abs | CMP abs | DEC abs | |
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| D- | BNE rel | CMP ind,Y | | | | CMP zpg,X | DEC zpg,X | | CLD impl | CMP abs,Y | | | | CMP abs,X | DEC abs,X | |
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| E- | CPX # | SBC X,ind | | | CPX zpg | SBC zpg | INC zpg | | INX impl | SBC # | NOP impl | | CPX abs | SBC abs | INC abs | |
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| F- | BEQ rel | SBC ind,Y | | | | SBC zpg,X | INC zpg,X | | SED impl | SBC abs,Y | | | | SBC abs,X | INC abs,X | |
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+----+----------+-----------+-------+----+-----------+-----------+-----------+----+----------+-----------+----------+----+-----------+-----------+-----------+----+
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#+end_src
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** Instruction encoding
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| 0-7 |
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|--------|
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| opcode |
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| 0-7 | 8-21 |
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|--------|---------------|
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| opcode | relative addr |
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| 0-7 | 8-15 | 16-X |
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|--------|------|-------|
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| opcode | attr | value |
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* Instruction Set
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| OP | ATTR | IMM | Size | Note |
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|----|------|----------|------|-------------------------------------|
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| 00 | | | 1 | Break |
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| 01 | | XXXX | 3 | Or with accumulator |
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| 08 | | | 1 | Push processor status |
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| 09 | 01 | XX | 3 | Or with accumulator |
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| 09 | 02 | XXXX | 4 | Or with accumulator |
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| 09 | 03 | XXXXXXXX | 6 | Or with accumulator |
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| 0A | | | 1 | Shift Left One Bit with accumulator |
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| 10 | | XXXX | 3 | Branch on plus |
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