From ecb434c419395981128e829622a5f328c5a8c082 Mon Sep 17 00:00:00 2001 From: d0p1 Date: Mon, 22 Apr 2024 08:51:15 +0200 Subject: [PATCH] Update isa --- doc/isa.org | 94 ++++++++++++++++++++++++++++++++++++----------------- 1 file changed, 65 insertions(+), 29 deletions(-) diff --git a/doc/isa.org b/doc/isa.org index ae353f0..dfca5bb 100644 --- a/doc/isa.org +++ b/doc/isa.org @@ -1,6 +1,11 @@ #+title: 65∞2 Instruction Set Architecture #+author: d0p1 +** Introduction + +- Op codes are 8 bits wide +- The minimum addressable data is 8bits wides + ** Registers - PC :: Program counter (32bit) @@ -31,13 +36,30 @@ Status register flags ** Control Registers +** Exception + +** Privileged Exception + +- IRQ +- Syscall +- Bus error + + +** Non-Privileged Exception + +- undefined op code +- undefined data type + ** Addressing Modes -*** Implied Addressing +*** Immediate -*** Remative Addressing +*** Implied + +*** Register + +*** 8 and 16 bit relative -*** Immediate Addressing A size and a literal operand is given immediately after the instruction. @@ -53,34 +75,36 @@ A size and a literal operand is given immediately after the instruction. ** Opcodes -| | -0 | -1 | -2 | -3 | -4 | -5 | -6 | -7 | -8 | -9 | -A | -B | -C | -D | -E | -F | -|----|----------|-----------|-------|--------|----|----|----|----|----------|-----------|----------|----|-----------|-----------|-----------|----| -| 0- | BRK impl | ORA X,ind | | prefix | | | | prefix | PHP impl | ORA # | ASL A | | | ORA abs | ASL abs | | -| 1- | BPL rel | ORA ind,Y | | prefix | | | | prefix | CLC impl | ORA abs,Y | | | | ORA abs,X | ASL abs,X | | -| 2- | JSR abs | AND X,ind | | prefix | | | | prefix | PLP impl | AND # | ROL A | | BIT abs | AND abs | ROL abs | | -| 3- | BMI rel | AND ind,Y | | prefix | | | | prefix | SEC impl | AND abs,Y | | | | AND abs,X | ROL abs,X | | -| 4- | RTI impl | EOR X,ind | | prefix | | | | prefix | PHA impl | EOR # | LSR A | | JMP abs | EOR abs | LSR abs | | -| 5- | BVC rel | EOR ind,Y | | prefix | | | | prefix | CLI impl | EOR abs,Y | | | | EOR abs,X | LSR abs,X | | -| 6- | RTS impl | ADC X,ind | PER? | prefix | | | | prefix | PLA impl | ADC # | ROR A | | JMP ind | ADC abs | ROR abs | | -| 7- | BVS rel | ADC ind,Y | | prefix | | | | prefix | SEI impl | ADC abs,Y | | | | ADC abs,X | ROR abs,X | | -| 8- | | STA X,ind | | prefix | | | | prefix | DEY impl | | TXA impl | | STY abs | STA abs | STX abs | | -| 9- | BCC rel | STA ind,Y | | prefix | | | | prefix | TYA impl | STA abs,Y | TXS impl | | | STA abs,X | | | -| A- | LDY # | LDA X,ind | LDX # | prefix | | | | prefix | TAY impl | LDA # | TAX impl | | LDY abs | LDA abs | LDX abs | | -| B- | BCS rel | LDA ind,Y | | prefix | | | | prefix | CLV impl | LDA abs,Y | TSX impl | | LDY abs,X | LDA abs,X | LDX abs,Y | | -| C- | CPY # | CMP X,ind | | prefix | | | | prefix | INY impl | CMP # | DEX impl | | CPY abs | CMP abs | DEC abs | | -| D- | BNE rel | CMP ind,Y | | prefix | | | | prefix | CLD impl | CMP abs,Y | | | | CMP abs,X | DEC abs,X | | -| E- | CPX # | SBC X,ind | | prefix | | | | prefix | INX impl | SBC # | NOP impl | | CPX abs | SBC abs | INC abs | | -| F- | BEQ rel | SBC ind,Y | | prefix | | | | prefix | SED impl | SBC abs,Y | | | | SBC abs,X | INC abs,X | | +| | -0 | -1 | -2 | -3 | -4 | -5 | -6 | -7 | -8 | -9 | -A | -B | -C | -D | -E | -F | +|----+---------------+---------------+-----------+-----------+----+----+----+-----------+-------+---------------+---------+----+---------------+---------------+-----------+----| +| 0- | *BRK* /#byte/ | *ORA* /X,ind/ | | /prefix1/ | | | | /prefix1/ | *PHP* | *ORA* /#/ | *ASL* A | | | *ORA* /abs/ | ASL abs | | +| 1- | *BPL* /rel/ | *ORA* /ind,Y/ | | /prefix1/ | | | | /prefix1/ | *CLC* | *ORA* /abs,Y/ | | | | *ORA* /abs,X/ | ASL abs,X | | +| 2- | *JSR* /abs/ | *AND* /X,ind/ | | /prefix1/ | | | | /prefix1/ | *PLP* | *AND* /#/ | *ROL* A | | *BIT* /abs/ | *AND* /abs/ | ROL abs | | +| 3- | *BMI* /rel/ | *AND* /ind,Y/ | | /prefix1/ | | | | /prefix1/ | *SEC* | *AND* /abs,Y/ | | | | *AND* /abs,X/ | ROL abs,X | | +| 4- | *RTI* | *EOR* /X,ind/ | | /prefix1/ | | | | /prefix1/ | *PHA* | *EOR* /#/ | *LSR* A | | *JMP* /abs/ | *EOR* /abs/ | LSR abs | | +| 5- | *BVC* /rel/ | *EOR* /ind,Y/ | | /prefix1/ | | | | /prefix1/ | *CLI* | *EOR* /abs,Y/ | | | | *EOR* /abs,X/ | LSR abs,X | | +| 6- | *RTS* | *ADC* /X,ind/ | PER? | /prefix1/ | | | | /prefix1/ | *PLA* | *ADC* /#/ | *ROR* A | | *JMP* /ind/ | *ADC* /abs/ | ROR abs | | +| 7- | *BVS* /rel/ | *ADC* /ind,Y/ | | /prefix1/ | | | | /prefix1/ | *SEI* | *ADC* /abs,Y/ | | | | *ADC* /abs,X/ | ROR abs,X | | +| 8- | | *STA* /X,ind/ | | /prefix1/ | | | | /prefix1/ | *DEY* | | *TXA* | | *STY* /abs/ | *STA* /abs/ | STX abs | | +| 9- | *BCC* /rel/ | *STA* /ind,Y/ | | /prefix1/ | | | | /prefix1/ | *TYA* | *STA* /abs,Y/ | *TXS* | | | *STA* /abs,X/ | | | +| A- | *LDY* /#/ | *LDA* /X,ind/ | *LDX* /#/ | /prefix1/ | | | | /prefix1/ | *TAY* | *LDA* /#/ | *TAX* | | *LDY* /abs/ | *LDA* /abs/ | LDX abs | | +| B- | *BCS* /rel/ | *LDA* /ind,Y/ | | /prefix1/ | | | | /prefix1/ | *CLV* | *LDA* /abs,Y/ | *TSX* | | *LDY* /abs,X/ | *LDA* /abs,X/ | LDX abs,Y | | +| C- | *CPY* /#/ | *CMP* /X,ind/ | | /prefix1/ | | | | /prefix1/ | *INY* | *CMP* /#/ | *DEX* | | *CPY* /abs/ | *CMP* /abs/ | DEC abs | | +| D- | *BNE* /rel/ | *CMP* /ind,Y/ | | /prefix1/ | | | | /prefix1/ | *CLD* | *CMP* /abs,Y/ | | | | *CMP* /abs,X/ | DEC abs,X | | +| E- | *CPX* /#/ | *SBC* /X,ind/ | | /prefix1/ | | | | /prefix1/ | *INX* | *SBC* /#/ | *NOP* | | *CPX* /abs/ | *SBC* /abs/ | INC abs | | +| F- | *BEQ* /rel/ | *SBC* /ind,Y/ | | /prefix1/ | | | | /prefix1/ | *SED* | *SBC* /abs,Y/ | | | | *SBC* /abs,X/ | INC abs,X | | ** Instruction encoding *** Prefix -| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | -|---|---|---|---|---|---|---|---| +**** Prefix 1 + +| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | +|---+---+----+----+---+---+---+---| | A | A | OS | OS | 0 | S | 1 | 1 | -- OS :: Size +- OS :: Operand Size - 00 8bit - 01 16bit - 10 32bit @@ -90,7 +114,7 @@ A size and a literal operand is given immediately after the instruction. #+begin_src - 8bits 8bits 8/16/32/64bits + 8bits 8bits 8/16/32/64bits +--------+--------+-------...---+ | prefix | opcode | value | +--------+--------+-------...---+ @@ -101,7 +125,7 @@ A size and a literal operand is given immediately after the instruction. ** Instructions Listing - ADC :: add with carry -- AND :: and (with accumulator) +- AND :: bitwise and with accumulator - ASL :: arithmetic shift left - BCC :: branch on carry clear - BCS :: branch on carry set @@ -109,6 +133,18 @@ A size and a literal operand is given immediately after the instruction. - BIT :: bitwise test with accumulator - BMI :: branch on minus - BNE :: branch not equal -- BPL :: Branch on plus -- BRK :: -- BSR :: +- BPL :: branch on plus +- BRK :: break / interrupt +- BVC :: branch on overflow clear +- BVS :: branch on overflow set +- CLC :: clear carry +- CLD :: clear decimal +- CLI :: disable interrupt +- CLV :: clear overflow + + +** Credits + +- [[http://www.6502.org/users/andre/65k/index.html][The 65k Project (André Fachat)]] +- [[https://web.archive.org/web/20221029042214if_/http://archive.6502.org/datasheets/mos_65e4_microprocessor_final_design_spec_may_10_1982.pdf][mos65e4]] +- [[http://www.mirkosoft.sk/65832.html]][WDC 65832] \ No newline at end of file