#+title: 65∞2 Instruction Set Architecture
#+author: d0p1

** Introduction

- Op codes are 8 bits wide
- The minimum addressable data is 8bits wides

** Registers

- PC :: Program counter (32bit)
- A  :: Accumulator (32bit)
- X  :: X index register (32bit)
- Y  :: Y index register (32bit)
- SR :: status register (8bit)
- SP :: stack pointer (32bit)

Status register flags

#+begin_src
 7                0
  +-+-+-+-+-+-+-+-+
  |N|V|0|B|D|0|Z|C|
  +-+-+-+-+-+-+-+-+
#+end_src

- N :: Negative
  The negative flag (N) indicates the presence of a set sign bit in bit-position 31.
- V :: Overflow
  The overflow flag (V) indicates overflow with signed binary arithmetics.
- B :: Break
- D :: Decimal
- Z :: Zero
  The zero flag (Z) indicates a value of all zero bits.
- C :: Carry

** Control Registers

** Exception

** Privileged Exception

- IRQ
- Syscall
- Bus error


** Non-Privileged Exception

- undefined op code
- undefined data type

** Addressing Modes

*** Immediate

*** Implied

*** Register

*** 8 and 16 bit relative


A size and a literal operand is given immediately after the instruction.

#+begin_src asm
  LDA.B #7
  LDA.W #300
  LDA.L #$DEADBEEF
  LDA.SB #-5         ! sign extended
  LDA.SW #-5367      ! sign extended
#+end_src

*** Absolute Addressing

** Opcodes

|    | -0            | -1            | -2        | -3        | -4 | -5 | -6 | -7        | -8    | -9            | -A      | -B | -C            | -D            | -E        | -F |
|----+---------------+---------------+-----------+-----------+----+----+----+-----------+-------+---------------+---------+----+---------------+---------------+-----------+----|
| 0- | *BRK* /#byte/ | *ORA* /X,ind/ |           | /prefix1/ |    |    |    | /prefix1/ | *PHP* | *ORA* /#/     | *ASL* A |    |               | *ORA* /abs/   | ASL abs   |    |
| 1- | *BPL* /rel/   | *ORA* /ind,Y/ |           | /prefix1/ |    |    |    | /prefix1/ | *CLC* | *ORA* /abs,Y/ |         |    |               | *ORA* /abs,X/ | ASL abs,X |    |
| 2- | *JSR* /abs/   | *AND* /X,ind/ |           | /prefix1/ |    |    |    | /prefix1/ | *PLP* | *AND* /#/     | *ROL* A |    | *BIT* /abs/   | *AND* /abs/   | ROL abs   |    |
| 3- | *BMI* /rel/   | *AND* /ind,Y/ |           | /prefix1/ |    |    |    | /prefix1/ | *SEC* | *AND* /abs,Y/ |         |    |               | *AND* /abs,X/ | ROL abs,X |    |
| 4- | *RTI*         | *EOR* /X,ind/ |           | /prefix1/ |    |    |    | /prefix1/ | *PHA* | *EOR* /#/     | *LSR* A |    | *JMP* /abs/   | *EOR* /abs/   | LSR abs   |    |
| 5- | *BVC* /rel/   | *EOR* /ind,Y/ |           | /prefix1/ |    |    |    | /prefix1/ | *CLI* | *EOR* /abs,Y/ |         |    |               | *EOR* /abs,X/ | LSR abs,X |    |
| 6- | *RTS*         | *ADC* /X,ind/ | PER?      | /prefix1/ |    |    |    | /prefix1/ | *PLA* | *ADC* /#/     | *ROR* A |    | *JMP* /ind/   | *ADC* /abs/   | ROR abs   |    |
| 7- | *BVS* /rel/   | *ADC* /ind,Y/ |           | /prefix1/ |    |    |    | /prefix1/ | *SEI* | *ADC* /abs,Y/ |         |    |               | *ADC* /abs,X/ | ROR abs,X |    |
| 8- |               | *STA* /X,ind/ |           | /prefix1/ |    |    |    | /prefix1/ | *DEY* |               | *TXA*   |    | *STY* /abs/   | *STA* /abs/   | STX abs   |    |
| 9- | *BCC* /rel/   | *STA* /ind,Y/ |           | /prefix1/ |    |    |    | /prefix1/ | *TYA* | *STA* /abs,Y/ | *TXS*   |    |               | *STA* /abs,X/ |           |    |
| A- | *LDY* /#/     | *LDA* /X,ind/ | *LDX* /#/ | /prefix1/ |    |    |    | /prefix1/ | *TAY* | *LDA* /#/     | *TAX*   |    | *LDY* /abs/   | *LDA* /abs/   | LDX abs   |    |
| B- | *BCS* /rel/   | *LDA* /ind,Y/ |           | /prefix1/ |    |    |    | /prefix1/ | *CLV* | *LDA* /abs,Y/ | *TSX*   |    | *LDY* /abs,X/ | *LDA* /abs,X/ | LDX abs,Y |    |
| C- | *CPY* /#/     | *CMP* /X,ind/ |           | /prefix1/ |    |    |    | /prefix1/ | *INY* | *CMP* /#/     | *DEX*   |    | *CPY* /abs/   | *CMP* /abs/   | DEC abs   |    |
| D- | *BNE* /rel/   | *CMP* /ind,Y/ |           | /prefix1/ |    |    |    | /prefix1/ | *CLD* | *CMP* /abs,Y/ |         |    |               | *CMP* /abs,X/ | DEC abs,X |    |
| E- | *CPX* /#/     | *SBC* /X,ind/ |           | /prefix1/ |    |    |    | /prefix1/ | *INX* | *SBC* /#/     | *NOP*   |    | *CPX* /abs/   | *SBC* /abs/   | INC abs   |    |
| F- | *BEQ* /rel/   | *SBC* /ind,Y/ |           | /prefix1/ |    |    |    | /prefix1/ | *SED* | *SBC* /abs,Y/ |         |    |               | *SBC* /abs,X/ | INC abs,X |    |

** Instruction encoding

*** Prefix

**** Prefix 1

| 7 | 6 |  5 |  4 | 3 | 2 | 1 | 0 |
|---+---+----+----+---+---+---+---|
| A | A | OS | OS | 0 | S | 1 | 1 |

- OS :: Operand Size
  - 00 8bit
  - 01 16bit
  - 10 32bit
  - 11 64bit
- A :: Address Size
- S :: sign-extension


#+begin_src
    8bits    8bits    8/16/32/64bits
  +--------+--------+-------...---+
  | prefix | opcode | value       |
  +--------+--------+-------...---+
#+end_src



** Instructions Listing

- ADC :: add with carry
- AND :: bitwise and with accumulator
- ASL :: arithmetic shift left
- BCC :: branch on carry clear
- BCS :: branch on carry set
- BEQ :: branch on equal (zero set)
- BIT :: bitwise test with accumulator
- BMI :: branch on minus
- BNE :: branch not equal
- BPL :: branch on plus
- BRK :: break / interrupt
- BVC :: branch on overflow clear
- BVS :: branch on overflow set
- CLC :: clear carry
- CLD :: clear decimal
- CLI :: disable interrupt
- CLV :: clear overflow


** Credits

- [[http://www.6502.org/users/andre/65k/index.html][The 65k Project (André Fachat)]]
- [[https://web.archive.org/web/20221029042214if_/http://archive.6502.org/datasheets/mos_65e4_microprocessor_final_design_spec_may_10_1982.pdf][mos65e4]]
- [[http://www.mirkosoft.sk/65832.html]][WDC 65832]