2019-07-27 10:44:24 +00:00
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//
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// low-level driver routines for 16550a UART.
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//
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2019-06-03 18:13:07 +00:00
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#include "types.h"
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#include "param.h"
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2019-05-31 13:45:59 +00:00
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#include "memlayout.h"
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2019-06-03 18:13:07 +00:00
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#include "riscv.h"
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#include "spinlock.h"
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2019-07-02 13:14:47 +00:00
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#include "proc.h"
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2019-06-03 18:13:07 +00:00
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#include "defs.h"
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2009-05-31 00:24:11 +00:00
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2019-07-27 10:44:24 +00:00
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// the UART control registers are memory-mapped
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// at address UART0. this macro returns the
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// address of one of the registers.
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#define Reg(reg) ((volatile unsigned char *)(UART0 + reg))
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2019-07-28 11:43:22 +00:00
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// the UART control registers.
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// some have different meanings for
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// read vs write.
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2020-07-20 10:59:26 +00:00
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// see http://byterunner.com/16550.html
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2020-07-23 10:27:20 +00:00
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#define RHR 0 // receive holding register (for input bytes)
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#define THR 0 // transmit holding register (for output bytes)
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#define IER 1 // interrupt enable register
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#define IER_TX_ENABLE (1<<0)
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#define IER_RX_ENABLE (1<<1)
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#define FCR 2 // FIFO control register
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#define FCR_FIFO_ENABLE (1<<0)
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#define FCR_FIFO_CLEAR (3<<1) // clear the content of the two FIFOs
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#define ISR 2 // interrupt status register
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#define LCR 3 // line control register
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#define LCR_EIGHT_BITS (3<<0)
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#define LCR_BAUD_LATCH (1<<7) // special mode to set baud rate
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#define LSR 5 // line status register
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#define LSR_RX_READY (1<<0) // input is waiting to be read from RHR
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#define LSR_TX_IDLE (1<<5) // THR can accept another character to send
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2009-05-31 00:24:11 +00:00
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2019-07-27 10:44:24 +00:00
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#define ReadReg(reg) (*(Reg(reg)))
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#define WriteReg(reg, v) (*(Reg(reg)) = (v))
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2009-05-31 00:24:11 +00:00
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2020-07-20 10:59:26 +00:00
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// the transmit output buffer.
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struct spinlock uart_tx_lock;
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#define UART_TX_BUF_SIZE 32
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char uart_tx_buf[UART_TX_BUF_SIZE];
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int uart_tx_w; // write next to uart_tx_buf[uart_tx_w++]
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int uart_tx_r; // read next from uart_tx_buf[uar_tx_r++]
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2020-08-28 09:51:48 +00:00
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extern volatile int panicked; // from printf.c
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2020-07-20 10:59:26 +00:00
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void uartstart();
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2009-05-31 00:24:11 +00:00
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void
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uartinit(void)
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{
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2019-07-27 10:44:24 +00:00
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// disable interrupts.
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WriteReg(IER, 0x00);
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2009-05-31 00:24:11 +00:00
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2019-07-27 10:44:24 +00:00
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// special mode to set baud rate.
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2020-07-23 10:27:20 +00:00
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WriteReg(LCR, LCR_BAUD_LATCH);
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2016-08-25 13:13:00 +00:00
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2019-07-27 10:44:24 +00:00
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// LSB for baud rate of 38.4K.
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WriteReg(0, 0x03);
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2009-05-31 00:24:11 +00:00
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2019-07-27 10:44:24 +00:00
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// MSB for baud rate of 38.4K.
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WriteReg(1, 0x00);
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2009-05-31 00:24:11 +00:00
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2019-05-31 13:45:59 +00:00
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// leave set-baud mode,
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// and set word length to 8 bits, no parity.
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2020-07-23 10:27:20 +00:00
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WriteReg(LCR, LCR_EIGHT_BITS);
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2016-08-25 13:13:00 +00:00
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2019-07-27 10:44:24 +00:00
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// reset and enable FIFOs.
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2020-07-23 10:27:20 +00:00
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WriteReg(FCR, FCR_FIFO_ENABLE | FCR_FIFO_CLEAR);
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2019-06-03 18:13:07 +00:00
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2020-07-20 10:59:26 +00:00
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// enable transmit and receive interrupts.
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2020-07-23 10:27:20 +00:00
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WriteReg(IER, IER_TX_ENABLE | IER_RX_ENABLE);
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2020-07-20 10:59:26 +00:00
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initlock(&uart_tx_lock, "uart");
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}
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// add a character to the output buffer and tell the
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// UART to start sending if it isn't already.
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2020-07-22 14:31:46 +00:00
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// blocks if the output buffer is full.
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// because it may block, it can't be called
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// from interrupts; it's only suitable for use
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// by write().
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2020-07-20 10:59:26 +00:00
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void
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2020-07-22 14:31:46 +00:00
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uartputc(int c)
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2020-07-20 10:59:26 +00:00
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{
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acquire(&uart_tx_lock);
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2020-08-28 09:51:48 +00:00
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if(panicked){
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for(;;)
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;
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}
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2020-07-20 10:59:26 +00:00
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while(1){
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if(((uart_tx_w + 1) % UART_TX_BUF_SIZE) == uart_tx_r){
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// buffer is full.
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2020-07-22 14:31:46 +00:00
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// wait for uartstart() to open up space in the buffer.
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sleep(&uart_tx_r, &uart_tx_lock);
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2020-07-20 10:59:26 +00:00
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} else {
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uart_tx_buf[uart_tx_w] = c;
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uart_tx_w = (uart_tx_w + 1) % UART_TX_BUF_SIZE;
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uartstart();
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release(&uart_tx_lock);
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return;
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}
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}
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2009-05-31 00:24:11 +00:00
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}
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2020-07-22 14:31:46 +00:00
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// alternate version of uartputc() that doesn't
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// use interrupts, for use by kernel printf() and
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// to echo characters. it spins waiting for the uart's
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// output register to be empty.
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void
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uartputc_sync(int c)
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{
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push_off();
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2020-08-28 09:51:48 +00:00
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if(panicked){
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for(;;)
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;
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}
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2020-07-22 14:31:46 +00:00
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// wait for Transmit Holding Empty to be set in LSR.
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2020-07-23 10:27:20 +00:00
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while((ReadReg(LSR) & LSR_TX_IDLE) == 0)
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2020-07-22 14:31:46 +00:00
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;
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WriteReg(THR, c);
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pop_off();
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}
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2020-07-20 10:59:26 +00:00
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// if the UART is idle, and a character is waiting
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// in the transmit buffer, send it.
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// caller must hold uart_tx_lock.
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// called from both the top- and bottom-half.
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2009-05-31 00:24:11 +00:00
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void
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2020-07-20 10:59:26 +00:00
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uartstart()
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2009-05-31 00:24:11 +00:00
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{
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2020-07-20 10:59:26 +00:00
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while(1){
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if(uart_tx_w == uart_tx_r){
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// transmit buffer is empty.
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return;
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}
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2020-07-23 10:27:20 +00:00
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if((ReadReg(LSR) & LSR_TX_IDLE) == 0){
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2020-07-20 10:59:26 +00:00
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// the UART transmit holding register is full,
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// so we cannot give it another byte.
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// it will interrupt when it's ready for a new byte.
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return;
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}
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int c = uart_tx_buf[uart_tx_r];
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uart_tx_r = (uart_tx_r + 1) % UART_TX_BUF_SIZE;
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// maybe uartputc() is waiting for space in the buffer.
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wakeup(&uart_tx_r);
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WriteReg(THR, c);
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}
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2009-05-31 00:24:11 +00:00
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}
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2019-07-27 09:47:19 +00:00
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// read one input character from the UART.
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// return -1 if none is waiting.
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2019-06-03 21:49:27 +00:00
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int
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2009-05-31 00:24:11 +00:00
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uartgetc(void)
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{
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2019-07-27 10:44:24 +00:00
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if(ReadReg(LSR) & 0x01){
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2019-06-03 21:49:27 +00:00
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// input data is ready.
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2019-07-27 10:44:24 +00:00
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return ReadReg(RHR);
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2019-06-03 21:49:27 +00:00
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} else {
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return -1;
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2019-06-03 21:59:17 +00:00
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}
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2009-05-31 00:24:11 +00:00
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}
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2020-07-20 10:59:26 +00:00
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// handle a uart interrupt, raised because input has
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// arrived, or the uart is ready for more output, or
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// both. called from trap.c.
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2009-05-31 00:24:11 +00:00
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void
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uartintr(void)
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{
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2020-07-20 10:59:26 +00:00
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// read and process incoming characters.
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2019-06-03 21:59:17 +00:00
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while(1){
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int c = uartgetc();
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if(c == -1)
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break;
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consoleintr(c);
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}
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2020-07-20 10:59:26 +00:00
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// send buffered characters.
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acquire(&uart_tx_lock);
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uartstart();
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release(&uart_tx_lock);
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2009-05-31 00:24:11 +00:00
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}
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