2019-07-27 10:44:24 +00:00
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//
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// low-level driver routines for 16550a UART.
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//
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2019-06-03 18:13:07 +00:00
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#include "types.h"
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#include "param.h"
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2019-05-31 13:45:59 +00:00
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#include "memlayout.h"
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2019-06-03 18:13:07 +00:00
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#include "riscv.h"
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#include "spinlock.h"
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2019-07-02 13:14:47 +00:00
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#include "proc.h"
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2019-06-03 18:13:07 +00:00
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#include "defs.h"
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2009-05-31 00:24:11 +00:00
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2019-07-27 10:44:24 +00:00
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// the UART control registers are memory-mapped
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// at address UART0. this macro returns the
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// address of one of the registers.
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#define Reg(reg) ((volatile unsigned char *)(UART0 + reg))
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2019-07-28 11:43:22 +00:00
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// the UART control registers.
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// some have different meanings for
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// read vs write.
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2019-05-31 13:45:59 +00:00
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// http://byterunner.com/16550.html
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2019-07-27 10:44:24 +00:00
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#define RHR 0 // receive holding register (for input bytes)
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#define THR 0 // transmit holding register (for output bytes)
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#define IER 1 // interrupt enable register
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#define FCR 2 // FIFO control register
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#define ISR 2 // interrupt status register
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#define LCR 3 // line control register
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#define LSR 5 // line status register
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2009-05-31 00:24:11 +00:00
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2019-07-27 10:44:24 +00:00
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#define ReadReg(reg) (*(Reg(reg)))
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#define WriteReg(reg, v) (*(Reg(reg)) = (v))
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2009-05-31 00:24:11 +00:00
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void
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uartinit(void)
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{
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2019-07-27 10:44:24 +00:00
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// disable interrupts.
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WriteReg(IER, 0x00);
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2009-05-31 00:24:11 +00:00
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2019-07-27 10:44:24 +00:00
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// special mode to set baud rate.
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WriteReg(LCR, 0x80);
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2016-08-25 13:13:00 +00:00
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2019-07-27 10:44:24 +00:00
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// LSB for baud rate of 38.4K.
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WriteReg(0, 0x03);
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2009-05-31 00:24:11 +00:00
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2019-07-27 10:44:24 +00:00
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// MSB for baud rate of 38.4K.
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WriteReg(1, 0x00);
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2009-05-31 00:24:11 +00:00
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2019-05-31 13:45:59 +00:00
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// leave set-baud mode,
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// and set word length to 8 bits, no parity.
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2019-07-27 10:44:24 +00:00
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WriteReg(LCR, 0x03);
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2016-08-25 13:13:00 +00:00
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2019-07-27 10:44:24 +00:00
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// reset and enable FIFOs.
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WriteReg(FCR, 0x07);
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2019-06-03 18:13:07 +00:00
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2019-07-27 10:44:24 +00:00
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// enable receive interrupts.
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WriteReg(IER, 0x01);
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2009-05-31 00:24:11 +00:00
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}
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2019-07-27 09:47:19 +00:00
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// write one output character to the UART.
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2009-05-31 00:24:11 +00:00
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void
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uartputc(int c)
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{
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2019-06-04 14:43:45 +00:00
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// wait for Transmit Holding Empty to be set in LSR.
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2019-07-27 10:44:24 +00:00
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while((ReadReg(LSR) & (1 << 5)) == 0)
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2019-06-04 14:43:45 +00:00
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;
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2019-07-27 10:44:24 +00:00
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WriteReg(THR, c);
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2009-05-31 00:24:11 +00:00
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}
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2019-07-27 09:47:19 +00:00
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// read one input character from the UART.
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// return -1 if none is waiting.
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2019-06-03 21:49:27 +00:00
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int
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2009-05-31 00:24:11 +00:00
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uartgetc(void)
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{
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2019-07-27 10:44:24 +00:00
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if(ReadReg(LSR) & 0x01){
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2019-06-03 21:49:27 +00:00
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// input data is ready.
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2019-07-27 10:44:24 +00:00
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return ReadReg(RHR);
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2019-06-03 21:49:27 +00:00
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} else {
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return -1;
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2019-06-03 21:59:17 +00:00
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}
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2009-05-31 00:24:11 +00:00
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}
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2019-07-27 09:47:19 +00:00
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// trap.c calls here when the uart interrupts.
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2009-05-31 00:24:11 +00:00
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void
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uartintr(void)
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{
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2019-06-03 21:59:17 +00:00
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while(1){
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int c = uartgetc();
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if(c == -1)
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break;
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consoleintr(c);
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}
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2009-05-31 00:24:11 +00:00
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}
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