2019-06-06 09:19:59 +00:00
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#include "types.h"
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#include "param.h"
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#include "memlayout.h"
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#include "riscv.h"
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#include "defs.h"
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//
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// the riscv Platform Level Interrupt Controller (PLIC).
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//
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void
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plicinit(void)
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{
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2019-06-13 10:49:02 +00:00
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// set desired IRQ priorities non-zero (otherwise disabled).
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2019-06-06 09:19:59 +00:00
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*(uint32*)(PLIC + UART0_IRQ*4) = 1;
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2019-06-13 13:40:17 +00:00
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*(uint32*)(PLIC + VIRTIO0_IRQ*4) = 1;
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2019-06-06 09:19:59 +00:00
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}
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void
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plicinithart(void)
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{
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int hart = cpuid();
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// set uart's enable bit for this hart's S-mode.
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2019-06-13 13:40:17 +00:00
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*(uint32*)PLIC_SENABLE(hart)= (1 << UART0_IRQ) | (1 << VIRTIO0_IRQ);
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2019-06-06 09:19:59 +00:00
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// set this hart's S-mode priority threshold to 0.
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*(uint32*)PLIC_SPRIORITY(hart) = 0;
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}
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// ask the PLIC what interrupt we should serve.
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int
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plic_claim(void)
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{
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int hart = cpuid();
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int irq = *(uint32*)PLIC_SCLAIM(hart);
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return irq;
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}
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// tell the PLIC we've served this IRQ.
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void
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plic_complete(int irq)
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{
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int hart = cpuid();
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*(uint32*)PLIC_SCLAIM(hart) = irq;
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}
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