comment nits

This commit is contained in:
Robert Morris 2022-08-09 14:17:46 -04:00
parent af9abaca05
commit 27a669ef25
4 changed files with 23 additions and 19 deletions

View file

@ -1,21 +1,21 @@
# qemu -kernel loads the kernel at 0x80000000
# and causes each CPU to jump there.
# qemu -kernel loads the kernel at 0x80000000
# and causes each hart (i.e. CPU) to jump there.
# kernel.ld causes the following code to
# be placed at 0x80000000.
.section .text
.global _entry
_entry:
# set up a stack for C.
# set up a stack for C.
# stack0 is declared in start.c,
# with a 4096-byte stack per CPU.
# sp = stack0 + (hartid * 4096)
la sp, stack0
li a0, 1024*4
csrr a1, mhartid
csrr a1, mhartid
addi a1, a1, 1
mul a0, a0, a1
add sp, sp, a0
# jump to start() in start.c
# jump to start() in start.c
call start
spin:
j spin

View file

@ -1,17 +1,19 @@
#
#
# interrupts and exceptions while in supervisor
# mode come here.
#
# push all registers, call kerneltrap(), restore, return.
# the current stack is a kernel stack.
# push all registers, call kerneltrap().
# when kerneltrap() returns, restore registers, return.
#
.globl kerneltrap
.globl kernelvec
.align 4
kernelvec:
// make room to save registers.
# make room to save registers.
addi sp, sp, -256
// save the registers.
# save the registers.
sd ra, 0(sp)
sd sp, 8(sp)
sd gp, 16(sp)
@ -44,14 +46,14 @@ kernelvec:
sd t5, 232(sp)
sd t6, 240(sp)
// call the C trap handler in trap.c
# call the C trap handler in trap.c
call kerneltrap
// restore registers.
# restore registers.
ld ra, 0(sp)
ld sp, 8(sp)
ld gp, 16(sp)
// not this, in case we moved CPUs: ld tp, 24(sp)
# not tp (contains hartid), in case we moved CPUs
ld t0, 32(sp)
ld t1, 40(sp)
ld t2, 48(sp)
@ -82,7 +84,7 @@ kernelvec:
addi sp, sp, 256
// return to whatever we were doing in the kernel.
# return to whatever we were doing in the kernel.
sret
#
@ -109,8 +111,9 @@ timervec:
add a3, a3, a2
sd a3, 0(a1)
# raise a supervisor software interrupt.
li a1, 2
# arrange for a supervisor software interrupt
# after this handler returns.
li a1, 2
csrw sip, a1
ld a3, 16(a0)

View file

@ -295,7 +295,7 @@ r_sp()
return x;
}
// read and write tp, the thread pointer, which holds
// read and write tp, the thread pointer, which xv6 uses to hold
// this core's hartid (core number), the index into cpus[].
static inline uint64
r_tp()
@ -342,7 +342,7 @@ typedef uint64 *pagetable_t; // 512 PTEs
#define PTE_R (1L << 1)
#define PTE_W (1L << 2)
#define PTE_X (1L << 3)
#define PTE_U (1L << 4) // 1 -> user can access
#define PTE_U (1L << 4) // user can access
// shift a physical address to the right place for a PTE.
#define PA2PTE(pa) ((((uint64)pa) >> 12) << 10)

View file

@ -54,8 +54,9 @@ start()
asm volatile("mret");
}
// set up to receive timer interrupts in machine mode,
// which arrive at timervec in kernelvec.S,
// arrange to receive timer interrupts.
// they will arrive in machine mode at
// at timervec in kernelvec.S,
// which turns them into software interrupts for
// devintr() in trap.c.
void