consistency.
This commit is contained in:
parent
5cb7877e0f
commit
5c596bb3a7
70
ioapic.c
70
ioapic.c
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@ -37,30 +37,31 @@ ioapic_init(void)
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uchar id;
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int i;
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if (ismp) {
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io = (struct ioapic*) IO_APIC_BASE;
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l = ioapic_read(io, IOAPIC_VER);
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nintr = ((l & IOART_VER_MAXREDIR) >> MAXREDIRSHIFT) + 1;
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id = ioapic_read(io, IOAPIC_ID) >> APIC_ID_SHIFT;
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if(id != ioapic_id)
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cprintf("ioapic_init: id isn't equal to ioapic_id; not a MP\n");
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for(i = 0; i < nintr; i++) {
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// active-hi and edge-triggered for ISA interrupts
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// Assume that pin 0 on the first I/O APIC is an ExtINT pin.
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// Assume that pins 1-15 are ISA interrupts
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l = ioapic_read(io, IOAPIC_REDTBL_LO(i));
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l = l & ~IOART_INTMASK; // allow INTs
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l |= IOART_INTMSET;
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l = l & ~IOART_INTPOL; // active hi
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l = l & ~IOART_TRGRMOD; // edgee triggered
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l = l & ~IOART_DELMOD; // fixed
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l = l & ~IOART_DESTMOD; // physical mode
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l = l | (IRQ_OFFSET + i); // vector
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ioapic_write(io, IOAPIC_REDTBL_LO(i), l);
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h = ioapic_read(io, IOAPIC_REDTBL_HI(i));
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h &= ~IOART_DEST;
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ioapic_write(io, IOAPIC_REDTBL_HI(i), h);
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}
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if (!ismp)
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return;
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io = (struct ioapic*) IO_APIC_BASE;
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l = ioapic_read(io, IOAPIC_VER);
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nintr = ((l & IOART_VER_MAXREDIR) >> MAXREDIRSHIFT) + 1;
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id = ioapic_read(io, IOAPIC_ID) >> APIC_ID_SHIFT;
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if(id != ioapic_id)
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cprintf("ioapic_init: id isn't equal to ioapic_id; not a MP\n");
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for(i = 0; i < nintr; i++) {
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// active-hi and edge-triggered for ISA interrupts
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// Assume that pin 0 on the first I/O APIC is an ExtINT pin.
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// Assume that pins 1-15 are ISA interrupts
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l = ioapic_read(io, IOAPIC_REDTBL_LO(i));
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l = l & ~IOART_INTMASK; // allow INTs
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l |= IOART_INTMSET;
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l = l & ~IOART_INTPOL; // active hi
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l = l & ~IOART_TRGRMOD; // edgee triggered
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l = l & ~IOART_DELMOD; // fixed
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l = l & ~IOART_DESTMOD; // physical mode
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l = l | (IRQ_OFFSET + i); // vector
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ioapic_write(io, IOAPIC_REDTBL_LO(i), l);
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h = ioapic_read(io, IOAPIC_REDTBL_HI(i));
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h &= ~IOART_DEST;
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ioapic_write(io, IOAPIC_REDTBL_HI(i), h);
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}
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}
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@ -70,14 +71,15 @@ ioapic_enable (int irq, int cpunum)
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uint l, h;
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struct ioapic *io;
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if (ismp) {
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io = (struct ioapic*) IO_APIC_BASE;
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l = ioapic_read(io, IOAPIC_REDTBL_LO(irq));
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l = l & ~IOART_INTMASK; // allow INTs
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ioapic_write(io, IOAPIC_REDTBL_LO(irq), l);
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h = ioapic_read(io, IOAPIC_REDTBL_HI(irq));
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h &= ~IOART_DEST;
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h |= (cpunum << APIC_ID_SHIFT);
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ioapic_write(io, IOAPIC_REDTBL_HI(irq), h);
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}
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if (!ismp)
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return;
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io = (struct ioapic*) IO_APIC_BASE;
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l = ioapic_read(io, IOAPIC_REDTBL_LO(irq));
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l = l & ~IOART_INTMASK; // allow INTs
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ioapic_write(io, IOAPIC_REDTBL_LO(irq), l);
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h = ioapic_read(io, IOAPIC_REDTBL_HI(irq));
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h &= ~IOART_DEST;
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h |= (cpunum << APIC_ID_SHIFT);
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ioapic_write(io, IOAPIC_REDTBL_HI(irq), h);
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}
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17
lapic.c
17
lapic.c
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@ -105,13 +105,14 @@ lapic_write(int r, int data)
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void
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lapic_timerinit(void)
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{
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if (lapicaddr) {
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lapic_write(LAPIC_TDCR, LAPIC_X1);
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lapic_write(LAPIC_TIMER, LAPIC_CLKIN | LAPIC_PERIODIC |
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(IRQ_OFFSET + IRQ_TIMER));
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lapic_write(LAPIC_TCCR, 10000000);
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lapic_write(LAPIC_TICR, 10000000);
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}
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if (!lapicaddr)
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return;
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lapic_write(LAPIC_TDCR, LAPIC_X1);
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lapic_write(LAPIC_TIMER, LAPIC_CLKIN | LAPIC_PERIODIC |
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(IRQ_OFFSET + IRQ_TIMER));
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lapic_write(LAPIC_TCCR, 10000000);
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lapic_write(LAPIC_TICR, 10000000);
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}
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void
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@ -126,7 +127,7 @@ lapic_init(int c)
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{
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uint r, lvt;
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if (lapicaddr == 0)
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if (!lapicaddr)
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return;
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lapic_write(LAPIC_DFR, 0xFFFFFFFF); // Set dst format register
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