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cleaner UART register interface

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This commit is contained in:
Robert Morris 2019-07-27 06:44:24 -04:00
parent a33f60fea3
commit 629faafa36
2 changed files with 41 additions and 27 deletions
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4
kernel/console.c
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@ -192,6 +192,8 @@ consoleinit(void)
uartinit(); uartinit();
devsw[CONSOLE].write = consolewrite; // connect read and write system calls
// to consoleread and consolewrite.
devsw[CONSOLE].read = consoleread; devsw[CONSOLE].read = consoleread;
devsw[CONSOLE].write = consolewrite;
} }

64
kernel/uart.c
View file

@ -1,3 +1,7 @@
//
// low-level driver routines for 16550a UART.
//
#include "types.h" #include "types.h"
#include "param.h" #include "param.h"
#include "memlayout.h" #include "memlayout.h"
@ -6,41 +10,49 @@
#include "proc.h" #include "proc.h"
#include "defs.h" #include "defs.h"
// // the UART control registers are memory-mapped
// qemu -machine virt has a 16550a UART // at address UART0. this macro returns the
// qemu/hw/riscv/virt.c // address of one of the registers.
// http://byterunner.com/16550.html #define Reg(reg) ((volatile unsigned char *)(UART0 + reg))
//
// caller should lock.
//
// address of one of the registers // the registers. some have different meanings for
#define R(reg) ((volatile unsigned char *)(UART0 + reg)) // read and write.
// http://byterunner.com/16550.html
#define RHR 0 // receive holding register (for input bytes)
#define THR 0 // transmit holding register (for output bytes)
#define IER 1 // interrupt enable register
#define FCR 2 // FIFO control register
#define ISR 2 // interrupt status register
#define LCR 3 // line control register
#define LSR 5 // line status register
#define ReadReg(reg) (*(Reg(reg)))
#define WriteReg(reg, v) (*(Reg(reg)) = (v))
void void
uartinit(void) uartinit(void)
{ {
// disable interrupts -- IER // disable interrupts.
*R(1) = 0x00; WriteReg(IER, 0x00);
// special mode to set baud rate // special mode to set baud rate.
*R(3) = 0x80; WriteReg(LCR, 0x80);
// LSB for baud rate of 38.4K // LSB for baud rate of 38.4K.
*R(0) = 0x03; WriteReg(0, 0x03);
// MSB for baud rate of 38.4K // MSB for baud rate of 38.4K.
*R(1) = 0x00; WriteReg(1, 0x00);
// leave set-baud mode, // leave set-baud mode,
// and set word length to 8 bits, no parity. // and set word length to 8 bits, no parity.
*R(3) = 0x03; WriteReg(LCR, 0x03);
// reset and enable FIFOs -- FCR. // reset and enable FIFOs.
*R(2) = 0x07; WriteReg(FCR, 0x07);
// enable receive interrupts -- IER. // enable receive interrupts.
*R(1) = 0x01; WriteReg(IER, 0x01);
} }
// write one output character to the UART. // write one output character to the UART.
@ -48,9 +60,9 @@ void
uartputc(int c) uartputc(int c)
{ {
// wait for Transmit Holding Empty to be set in LSR. // wait for Transmit Holding Empty to be set in LSR.
while((*R(5) & (1 << 5)) == 0) while((ReadReg(LSR) & (1 << 5)) == 0)
; ;
*R(0) = c; WriteReg(THR, c);
} }
// read one input character from the UART. // read one input character from the UART.
@ -58,9 +70,9 @@ uartputc(int c)
int int
uartgetc(void) uartgetc(void)
{ {
if(*R(5) & 0x01){ if(ReadReg(LSR) & 0x01){
// input data is ready. // input data is ready.
return *R(0); return ReadReg(RHR);
} else { } else {
return -1; return -1;
} }