From 6781ac00366e2c46c0a4ed18dfd60e41a3fa4ae6 Mon Sep 17 00:00:00 2001
From: Matt Harvey <matt@teamdawg.org>
Date: Mon, 14 Sep 2020 14:49:57 -0700
Subject: [PATCH] Corrects order of UART RX/TX interrupt enable bits

(per http://byterunner.com/16550.html and manually tested in qemu bare metal echo)
---
 kernel/uart.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/kernel/uart.c b/kernel/uart.c
index ce89615..d586ea4 100644
--- a/kernel/uart.c
+++ b/kernel/uart.c
@@ -22,8 +22,8 @@
 #define RHR 0                 // receive holding register (for input bytes)
 #define THR 0                 // transmit holding register (for output bytes)
 #define IER 1                 // interrupt enable register
-#define IER_TX_ENABLE (1<<0)
-#define IER_RX_ENABLE (1<<1)
+#define IER_RX_ENABLE (1<<0)
+#define IER_TX_ENABLE (1<<1)
 #define FCR 2                 // FIFO control register
 #define FCR_FIFO_ENABLE (1<<0)
 #define FCR_FIFO_CLEAR (3<<1) // clear the content of the two FIFOs