nits
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0b6ab8416e
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3
ioapic.c
3
ioapic.c
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@ -46,7 +46,7 @@ ioapic_init(void)
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for (i = 0; i < nintr; i++) {
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for (i = 0; i < nintr; i++) {
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// active-hi and edge-triggered for ISA interrupts
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// active-hi and edge-triggered for ISA interrupts
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// Assume that pin 0 on the first I/O APIC is an ExtINT pin.
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// Assume that pin 0 on the first I/O APIC is an ExtINT pin.
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// Assume that pins 1-15 are ISA interrupts and that all
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// Assume that pins 1-15 are ISA interrupts
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l = ioapic_read(io, IOAPIC_REDTBL_LO(i));
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l = ioapic_read(io, IOAPIC_REDTBL_LO(i));
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l = l & ~IOART_INTMASK; // allow INTs
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l = l & ~IOART_INTMASK; // allow INTs
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l |= IOART_INTMSET;
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l |= IOART_INTMSET;
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@ -59,7 +59,6 @@ ioapic_init(void)
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h = ioapic_read(io, IOAPIC_REDTBL_HI(i));
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h = ioapic_read(io, IOAPIC_REDTBL_HI(i));
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h &= ~IOART_DEST;
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h &= ~IOART_DEST;
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ioapic_write(io, IOAPIC_REDTBL_HI(i), h);
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ioapic_write(io, IOAPIC_REDTBL_HI(i), h);
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// cprintf("intr %d: lo 0x%x hi 0x%x\n", i, l, h);
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}
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}
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}
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}
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14
trap.c
14
trap.c
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@ -79,12 +79,16 @@ trap(struct trapframe *tf)
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return;
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return;
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}
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}
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cprintf("trap %d from cpu %d eip %x\n", v, cpu(), tf->eip);
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if(v == (IRQ_OFFSET + IRQ_SPURIOUS)){
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cprintf("spurious interrupt from cpu %d eip %x\n", cpu(), tf->eip);
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return; // no eoi for this one.
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}
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if(curproc[cpu()]) {
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if(curproc[cpu()]) {
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cprintf("pid %d\n", curproc[cpu()]->pid);
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cprintf("pid %d: unhandled trap %d on cpu %d eip %x---terminate process\n",
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curproc[cpu()]->pid, v, cpu(), tf->eip);
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proc_exit();
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proc_exit();
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}
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}
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// panic("trap");
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cprintf("unexpected trap %d from cpu %d eip %x\n", v, cpu(), tf->eip);
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panic("trap");
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return;
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}
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}
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