checkpoint
This commit is contained in:
rtm
parent
be0a7eacda
commit
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2
Makefile
2
Makefile
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@ -1,5 +1,5 @@
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OBJS = main.o console.o string.o kalloc.o proc.o trapasm.o trap.o vectors.o \
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syscall.o
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syscall.o ide.o picirq.o
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CC = i386-jos-elf-gcc
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LD = i386-jos-elf-ld
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4
defs.h
4
defs.h
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@ -24,3 +24,7 @@ void * memset(void *dst, int c, unsigned n);
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// syscall.c
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void syscall(void);
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// picirq.c
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void irq_setmask_8259A(uint16_t mask);
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void pic_init(void);
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117
ide.c
Normal file
117
ide.c
Normal file
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@ -0,0 +1,117 @@
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/*
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* Minimal PIO-based (non-interrupt-driven) IDE driver code.
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* For information about what all this IDE/ATA magic means,
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* see the materials available on the class references page.
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*/
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#include "types.h"
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#include "param.h"
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#include "mmu.h"
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#include "proc.h"
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#include "defs.h"
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#include "x86.h"
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#define IDE_BSY 0x80
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#define IDE_DRDY 0x40
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#define IDE_DF 0x20
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#define IDE_ERR 0x01
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static int diskno = 0;
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static int
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ide_wait_ready(int check_error)
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{
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int r;
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while (((r = inb(0x1F7)) & (IDE_BSY|IDE_DRDY)) != IDE_DRDY)
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/* do nothing */;
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if (check_error && (r & (IDE_DF|IDE_ERR)) != 0)
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return -1;
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return 0;
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}
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int
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ide_probe_disk1(void)
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{
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int r, x;
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// wait for Device 0 to be ready
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ide_wait_ready(0);
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// switch to Device 1
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outb(0x1F6, 0xE0 | (1<<4));
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// check for Device 1 to be ready for a while
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for (x = 0; x < 1000 && (r = inb(0x1F7)) == 0; x++)
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/* do nothing */;
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// switch back to Device 0
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outb(0x1F6, 0xE0 | (0<<4));
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cprintf("Device 1 presence: %d\n", (x < 1000));
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return (x < 1000);
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}
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void
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ide_set_disk(int d)
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{
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if (d != 0 && d != 1)
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panic("bad disk number");
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diskno = d;
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}
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int
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ide_read(uint32_t secno, void *dst, unsigned nsecs)
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{
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int r;
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if(nsecs > 256)
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panic("ide_read");
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ide_wait_ready(0);
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outb(0x3f6, 0);
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outb(0x1F2, nsecs);
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outb(0x1F3, secno & 0xFF);
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outb(0x1F4, (secno >> 8) & 0xFF);
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outb(0x1F5, (secno >> 16) & 0xFF);
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outb(0x1F6, 0xE0 | ((diskno&1)<<4) | ((secno>>24)&0x0F));
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outb(0x1F7, 0x20); // CMD 0x20 means read sector
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sleep(0);
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for (; nsecs > 0; nsecs--, dst += 512) {
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if ((r = ide_wait_ready(1)) < 0)
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return r;
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insl(0x1F0, dst, 512/4);
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}
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return 0;
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}
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int
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ide_write(uint32_t secno, const void *src, unsigned nsecs)
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{
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int r;
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if(nsecs > 256)
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panic("ide_write");
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ide_wait_ready(0);
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outb(0x1F2, nsecs);
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outb(0x1F3, secno & 0xFF);
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outb(0x1F4, (secno >> 8) & 0xFF);
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outb(0x1F5, (secno >> 16) & 0xFF);
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outb(0x1F6, 0xE0 | ((diskno&1)<<4) | ((secno>>24)&0x0F));
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outb(0x1F7, 0x30); // CMD 0x30 means write sector
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for (; nsecs > 0; nsecs--, src += 512) {
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if ((r = ide_wait_ready(1)) < 0)
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return r;
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outsl(0x1F0, src, 512/4);
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}
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return 0;
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}
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20
main.c
20
main.c
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@ -9,6 +9,8 @@
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extern char edata[], end[];
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char buf[512];
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int
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main()
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{
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@ -18,16 +20,11 @@ main()
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// clear BSS
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memset(edata, 0, end - edata);
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// partially initizialize PIC
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outb(0x20+1, 0xFF); // IO_PIC1
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outb(0xA0+1, 0xFF); // IO_PIC2
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outb(0x20, 0x11);
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outb(0x20+1, 32);
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cprintf("\nxV6\n\n");
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kinit(); // physical memory allocator
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tinit(); // traps and interrupts
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pic_init();
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// create fake process zero
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p = &proc[0];
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@ -46,6 +43,16 @@ main()
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p->ppid = 0;
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setupsegs(p);
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// turn on interrupts
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write_eflags(read_eflags() | FL_IF);
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irq_setmask_8259A(0);
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#if 1
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ide_read(0, buf, 1);
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cprintf("sec0.0 %x\n", buf[0] & 0xff);
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#endif
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#if 0
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p = newproc();
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i = 0;
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@ -73,6 +80,7 @@ main()
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p->mem[i++] = T_SYSCALL;
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p->tf->tf_eip = 0;
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p->tf->tf_esp = p->sz;
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#endif
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swtch();
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92
picirq.c
Normal file
92
picirq.c
Normal file
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@ -0,0 +1,92 @@
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/* See COPYRIGHT for copyright information. */
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#include "types.h"
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#include "x86.h"
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#include "defs.h"
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#define MAX_IRQS 16 // Number of IRQs
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// I/O Addresses of the two 8259A programmable interrupt controllers
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#define IO_PIC1 0x20 // Master (IRQs 0-7)
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#define IO_PIC2 0xA0 // Slave (IRQs 8-15)
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#define IRQ_SLAVE 2 // IRQ at which slave connects to master
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#define IRQ_OFFSET 32 // IRQ 0 corresponds to int IRQ_OFFSET
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// Current IRQ mask.
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// Initial IRQ mask has interrupt 2 enabled (for slave 8259A).
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uint16_t irq_mask_8259A = 0xFFFF & ~(1<<IRQ_SLAVE);
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static int didinit;
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/* Initialize the 8259A interrupt controllers. */
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void
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pic_init(void)
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{
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didinit = 1;
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// mask all interrupts
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outb(IO_PIC1+1, 0xFF);
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outb(IO_PIC2+1, 0xFF);
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// Set up master (8259A-1)
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// ICW1: 0001g0hi
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// g: 0 = edge triggering, 1 = level triggering
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// h: 0 = cascaded PICs, 1 = master only
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// i: 0 = no ICW4, 1 = ICW4 required
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outb(IO_PIC1, 0x11);
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// ICW2: Vector offset
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outb(IO_PIC1+1, IRQ_OFFSET);
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// ICW3: bit mask of IR lines connected to slave PICs (master PIC),
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// 3-bit No of IR line at which slave connects to master(slave PIC).
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outb(IO_PIC1+1, 1<<IRQ_SLAVE);
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// ICW4: 000nbmap
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// n: 1 = special fully nested mode
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// b: 1 = buffered mode
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// m: 0 = slave PIC, 1 = master PIC
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// (ignored when b is 0, as the master/slave role
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// can be hardwired).
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// a: 1 = Automatic EOI mode
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// p: 0 = MCS-80/85 mode, 1 = intel x86 mode
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outb(IO_PIC1+1, 0x3);
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// Set up slave (8259A-2)
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outb(IO_PIC2, 0x11); // ICW1
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outb(IO_PIC2+1, IRQ_OFFSET + 8); // ICW2
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outb(IO_PIC2+1, IRQ_SLAVE); // ICW3
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// NB Automatic EOI mode doesn't tend to work on the slave.
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// Linux source code says it's "to be investigated".
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outb(IO_PIC2+1, 0x01); // ICW4
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// OCW3: 0ef01prs
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// ef: 0x = NOP, 10 = clear specific mask, 11 = set specific mask
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// p: 0 = no polling, 1 = polling mode
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// rs: 0x = NOP, 10 = read IRR, 11 = read ISR
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outb(IO_PIC1, 0x68); /* clear specific mask */
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outb(IO_PIC1, 0x0a); /* read IRR by default */
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outb(IO_PIC2, 0x68); /* OCW3 */
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outb(IO_PIC2, 0x0a); /* OCW3 */
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if (irq_mask_8259A != 0xFFFF)
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irq_setmask_8259A(irq_mask_8259A);
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}
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void
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irq_setmask_8259A(uint16_t mask)
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{
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int i;
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irq_mask_8259A = mask;
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if (!didinit)
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return;
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outb(IO_PIC1+1, (char)mask);
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outb(IO_PIC2+1, (char)(mask >> 8));
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cprintf("enabled interrupts:");
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for (i = 0; i < 16; i++)
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if (~mask & (1<<i))
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cprintf(" %d", i);
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cprintf("\n");
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}
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