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Merge branch 'riscv' of g.csail.mit.edu:xv6-dev into riscv

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This commit is contained in:
Robert Morris 2022-08-09 13:41:51 -04:00
parent 3abd7a16dd cf0c095721
commit af9abaca05
2 changed files with 0 additions and 8 deletions
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1
kernel/proc.h
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@ -31,7 +31,6 @@ extern struct cpu cpus[NCPU];
// per-process data for the trap handling code in trampoline.S. // per-process data for the trap handling code in trampoline.S.
// sits in a page by itself just under the trampoline page in the // sits in a page by itself just under the trampoline page in the
// user page table. not specially mapped in the kernel page table. // user page table. not specially mapped in the kernel page table.
// the sscratch register points here.
// uservec in trampoline.S saves user registers in the trapframe, // uservec in trampoline.S saves user registers in the trapframe,
// then initializes registers from the trapframe's // then initializes registers from the trapframe's
// kernel_sp, kernel_hartid, kernel_satp, and jumps to kernel_trap. // kernel_sp, kernel_hartid, kernel_satp, and jumps to kernel_trap.

7
kernel/riscv.h
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@ -217,13 +217,6 @@ r_satp()
return x; return x;
} }
// Supervisor Scratch register, for early trap handler in trampoline.S.
static inline void
w_sscratch(uint64 x)
{
asm volatile("csrw sscratch, %0" : : "r" (x));
}
static inline void static inline void
w_mscratch(uint64 x) w_mscratch(uint64 x)
{ {