kill TLB shoot down code
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de40730dad
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5 changed files with 0 additions and 49 deletions
1
defs.h
1
defs.h
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@ -73,7 +73,6 @@ int cpunum(void);
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extern volatile uint* lapic;
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extern volatile uint* lapic;
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void lapiceoi(void);
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void lapiceoi(void);
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void lapicinit(int);
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void lapicinit(int);
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void lapic_tlbflush(uint);
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void lapicstartap(uchar, uint);
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void lapicstartap(uchar, uint);
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void microdelay(int);
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void microdelay(int);
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38
lapic.c
38
lapic.c
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@ -47,27 +47,6 @@ lapicw(int index, int value)
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lapic[ID]; // wait for write to finish, by reading
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lapic[ID]; // wait for write to finish, by reading
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}
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}
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static uint
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lapicr(uint off)
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{
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return lapic[off];
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}
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static int
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apic_icr_wait()
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{
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uint i = 100000;
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while ((lapicr(ICRLO) & BUSY) != 0) {
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nop_pause();
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i--;
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if (i == 0) {
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cprintf("apic_icr_wait: wedged?\n");
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return -1;
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}
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}
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return 0;
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}
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//PAGEBREAK!
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//PAGEBREAK!
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void
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void
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lapicinit(int c)
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lapicinit(int c)
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@ -151,23 +130,6 @@ microdelay(int us)
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{
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{
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}
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}
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// Send IPI
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void
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lapic_ipi(int cpu, int ino)
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{
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lapicw(ICRHI, cpu << 24);
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lapicw(ICRLO, FIXED | DEASSERT | ino);
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if (apic_icr_wait() < 0)
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panic("lapic_ipi: icr_wait failure");
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}
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void
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lapic_tlbflush(uint cpu)
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{
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lapic_ipi(cpu, T_TLBFLUSH);
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}
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#define IO_RTC 0x70
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#define IO_RTC 0x70
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// Start additional processor running bootstrap code at addr.
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// Start additional processor running bootstrap code at addr.
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4
trap.c
4
trap.c
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@ -73,10 +73,6 @@ trap(struct trapframe *tf)
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cpu->id, tf->cs, tf->eip);
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cpu->id, tf->cs, tf->eip);
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lapiceoi();
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lapiceoi();
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break;
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break;
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case T_TLBFLUSH:
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lapiceoi();
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lcr3(rcr3());
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break;
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//PAGEBREAK: 13
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//PAGEBREAK: 13
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default:
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default:
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1
traps.h
1
traps.h
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@ -25,7 +25,6 @@
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// These are arbitrarily chosen, but with care not to overlap
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// These are arbitrarily chosen, but with care not to overlap
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// processor defined exceptions or interrupt vectors.
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// processor defined exceptions or interrupt vectors.
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#define T_SYSCALL 64 // system call
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#define T_SYSCALL 64 // system call
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#define T_TLBFLUSH 65 // flush TLB
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#define T_DEFAULT 500 // catchall
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#define T_DEFAULT 500 // catchall
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#define T_IRQ0 32 // IRQ 0 corresponds to int T_IRQ
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#define T_IRQ0 32 // IRQ 0 corresponds to int T_IRQ
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5
vm.c
5
vm.c
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@ -137,11 +137,6 @@ loadvm(struct proc *p)
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lcr3(PADDR(p->pgdir)); // switch to new address space
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lcr3(PADDR(p->pgdir)); // switch to new address space
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popcli();
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popcli();
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// Conservatively flush other processor's TLBs
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// XXX lazy--just 2 cpus, but xv6 doesn't need shootdown anyway.
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if (cpu->id == 0) lapic_tlbflush(1);
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else lapic_tlbflush(0);
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}
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}
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// Setup kernel part of a page table. Linear adresses map one-to-one
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// Setup kernel part of a page table. Linear adresses map one-to-one
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