Corrects order of UART RX/TX interrupt enable bits

(per http://byterunner.com/16550.html and manually tested in qemu bare metal echo)
This commit is contained in:
Matt Harvey 2020-09-14 14:49:57 -07:00 committed by Frans Kaashoek
parent b96547403d
commit b9359c3533

View file

@ -22,8 +22,8 @@
#define RHR 0 // receive holding register (for input bytes)
#define THR 0 // transmit holding register (for output bytes)
#define IER 1 // interrupt enable register
#define IER_TX_ENABLE (1<<0)
#define IER_RX_ENABLE (1<<1)
#define IER_RX_ENABLE (1<<0)
#define IER_TX_ENABLE (1<<1)
#define FCR 2 // FIFO control register
#define FCR_FIFO_ENABLE (1<<0)
#define FCR_FIFO_CLEAR (3<<1) // clear the content of the two FIFOs