better interrupt plan---this one appears to work
ioapic
This commit is contained in:
kaashoek
parent
32630628a9
commit
c8b29f6d03
1
Makefile
1
Makefile
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@ -4,6 +4,7 @@ OBJS = \
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ide.o\
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kalloc.o\
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lapic.o\
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ioapic.o\
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main.o\
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mp.o\
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picirq.o\
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2
bio.c
2
bio.c
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@ -43,7 +43,7 @@ bread(uint dev, uint sector)
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acquire(&ide_lock);
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c = ide_start_read(dev & 0xff, sector, b->data, 1);
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// sleep (c, &ide_lock);
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sleep (c, &ide_lock);
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ide_finish_read(c);
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release(&ide_lock);
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6
defs.h
6
defs.h
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@ -57,8 +57,14 @@ void lapic_timerinit(void);
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void lapic_timerintr(void);
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void lapic_enableintr(void);
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void lapic_disableintr(void);
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void lapic_eoi(void);
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int cpu(void);
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// ioapic
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extern uchar ioapic_id;
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void ioapic_init(void);
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void ioapic_enable (int irq, int cpu);
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// spinlock.c
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struct spinlock;
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void acquire(struct spinlock*);
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8
ide.c
8
ide.c
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@ -45,9 +45,12 @@ ide_wait_ready(int check_error)
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void
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ide_init(void)
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{
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cprintf("ide_init: enable IRQ 14\n");
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irq_setmask_8259A(irq_mask_8259A & ~(1<<14));
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if (ncpu < 2) {
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panic ("ide_init: disk interrupt is going to the second cpu\n");
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}
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ioapic_enable (14, 1); // 14 is IRQ # for IDE
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ide_wait_ready(0);
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cprintf ("ide_init:done\n");
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}
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void
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@ -57,6 +60,7 @@ ide_intr(void)
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cprintf("%d: ide_intr\n", cpu());
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wakeup(&request[tail]);
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release(&ide_lock);
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lapic_eoi();
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}
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int
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82
ioapic.c
Normal file
82
ioapic.c
Normal file
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@ -0,0 +1,82 @@
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#include "types.h"
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#include "mp.h"
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#include "defs.h"
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#include "x86.h"
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#include "traps.h"
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#include "ioapic.h"
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struct ioapic {
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uint ioregsel; uint p01; uint p02; uint p03;
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uint iowin; uint p11; uint p12; uint p13;
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};
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#define IOAPIC_REDTBL_LO(i) (IOAPIC_REDTBL + (i) * 2)
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#define IOAPIC_REDTBL_HI(i) (IOAPIC_REDTBL_LO(i) + 1)
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static uint
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ioapic_read(struct ioapic *io, int reg)
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{
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io->ioregsel = reg;
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return (io->iowin);
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}
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static void
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ioapic_write(struct ioapic *io, int reg, uint val)
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{
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io->ioregsel = reg;
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io->iowin = val;
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}
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void
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ioapic_init(void)
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{
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struct ioapic *io;
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uint l, h;
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int nintr;
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uchar id;
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int i;
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io = (struct ioapic *) IO_APIC_BASE;
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l = ioapic_read(io, IOAPIC_VER);
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nintr = ((l & IOART_VER_MAXREDIR) >> MAXREDIRSHIFT) + 1;
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id = ioapic_read(io, IOAPIC_ID) >> APIC_ID_SHIFT;
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if (id != ioapic_id)
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panic ("ioapic_init: id isn't equal to ioapic_id\n");
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cprintf ("ioapic VER: 0x%x id %d nintr %d\n", l, id, nintr);
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for (i = 0; i < nintr; i++) {
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// active-hi and edge-triggered for ISA interrupts
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// Assume that pin 0 on the first I/O APIC is an ExtINT pin.
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// Assume that pins 1-15 are ISA interrupts and that all
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l = ioapic_read(io, IOAPIC_REDTBL_LO(i));
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l = l & ~IOART_INTMASK; // allow INTs
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l |= IOART_INTMSET;
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l = l & ~IOART_INTPOL; // active hi
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l = l & ~IOART_TRGRMOD; // edgee triggered
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l = l & ~IOART_DELMOD; // fixed
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l = l & ~IOART_DESTMOD; // physical mode
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l = l | (IRQ_OFFSET + i); // vector
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ioapic_write(io, IOAPIC_REDTBL_LO(i), l);
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h = ioapic_read(io, IOAPIC_REDTBL_HI(i));
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h &= ~IOART_DEST;
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ioapic_write(io, IOAPIC_REDTBL_HI(i), h);
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// cprintf("intr %d: lo 0x%x hi 0x%x\n", i, l, h);
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}
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}
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void
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ioapic_enable (int irq, int cpu)
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{
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uint l, h;
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struct ioapic *io;
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io = (struct ioapic *) IO_APIC_BASE;
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l = ioapic_read(io, IOAPIC_REDTBL_LO(irq));
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l = l & ~IOART_INTMASK; // allow INTs
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ioapic_write(io, IOAPIC_REDTBL_LO(irq), l);
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h = ioapic_read(io, IOAPIC_REDTBL_HI(irq));
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h &= ~IOART_DEST;
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h |= (cpu << APIC_ID_SHIFT); // for fun, disk interrupts to cpu 1
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ioapic_write(io, IOAPIC_REDTBL_HI(irq), h);
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cprintf("intr %d: lo 0x%x hi 0x%x\n", irq, l, h);
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}
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90
ioapic.h
Normal file
90
ioapic.h
Normal file
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@ -0,0 +1,90 @@
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#define IO_APIC_BASE 0xFEC00000 /* default physical locations of an IO APIC */
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#define IOAPIC_WINDOW 0x10 /* window register offset */
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/* constants relating to APIC ID registers */
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#define APIC_ID_MASK 0xff000000
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#define APIC_ID_SHIFT 24
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#define APIC_ID_CLUSTER 0xf0
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#define APIC_ID_CLUSTER_ID 0x0f
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#define APIC_MAX_CLUSTER 0xe
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#define APIC_MAX_INTRACLUSTER_ID 3
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#define APIC_ID_CLUSTER_SHIFT 4
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/* fields in VER */
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#define APIC_VER_VERSION 0x000000ff
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#define APIC_VER_MAXLVT 0x00ff0000
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#define MAXLVTSHIFT 16
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/* Indexes into IO APIC */
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#define IOAPIC_ID 0x00
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#define IOAPIC_VER 0x01
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#define IOAPIC_ARB 0x02
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#define IOAPIC_REDTBL 0x10
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#define IOAPIC_REDTBL0 IOAPIC_REDTBL
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#define IOAPIC_REDTBL1 (IOAPIC_REDTBL+0x02)
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#define IOAPIC_REDTBL2 (IOAPIC_REDTBL+0x04)
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#define IOAPIC_REDTBL3 (IOAPIC_REDTBL+0x06)
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#define IOAPIC_REDTBL4 (IOAPIC_REDTBL+0x08)
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#define IOAPIC_REDTBL5 (IOAPIC_REDTBL+0x0a)
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#define IOAPIC_REDTBL6 (IOAPIC_REDTBL+0x0c)
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#define IOAPIC_REDTBL7 (IOAPIC_REDTBL+0x0e)
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#define IOAPIC_REDTBL8 (IOAPIC_REDTBL+0x10)
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#define IOAPIC_REDTBL9 (IOAPIC_REDTBL+0x12)
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#define IOAPIC_REDTBL10 (IOAPIC_REDTBL+0x14)
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#define IOAPIC_REDTBL11 (IOAPIC_REDTBL+0x16)
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#define IOAPIC_REDTBL12 (IOAPIC_REDTBL+0x18)
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#define IOAPIC_REDTBL13 (IOAPIC_REDTBL+0x1a)
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#define IOAPIC_REDTBL14 (IOAPIC_REDTBL+0x1c)
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#define IOAPIC_REDTBL15 (IOAPIC_REDTBL+0x1e)
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#define IOAPIC_REDTBL16 (IOAPIC_REDTBL+0x20)
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#define IOAPIC_REDTBL17 (IOAPIC_REDTBL+0x22)
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#define IOAPIC_REDTBL18 (IOAPIC_REDTBL+0x24)
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#define IOAPIC_REDTBL19 (IOAPIC_REDTBL+0x26)
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#define IOAPIC_REDTBL20 (IOAPIC_REDTBL+0x28)
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#define IOAPIC_REDTBL21 (IOAPIC_REDTBL+0x2a)
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#define IOAPIC_REDTBL22 (IOAPIC_REDTBL+0x2c)
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#define IOAPIC_REDTBL23 (IOAPIC_REDTBL+0x2e)
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/*
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* fields in the IO APIC's redirection table entries
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*/
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#define IOART_DEST APIC_ID_MASK /* broadcast addr: all APICs */
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#define IOART_RESV 0x00fe0000 /* reserved */
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#define IOART_INTMASK 0x00010000 /* R/W: INTerrupt mask */
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#define IOART_INTMCLR 0x00000000 /* clear, allow INTs */
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#define IOART_INTMSET 0x00010000 /* set, inhibit INTs */
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#define IOART_TRGRMOD 0x00008000 /* R/W: trigger mode */
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#define IOART_TRGREDG 0x00000000 /* edge */
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#define IOART_TRGRLVL 0x00008000 /* level */
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#define IOART_REM_IRR 0x00004000 /* RO: remote IRR */
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#define IOART_INTPOL 0x00002000 /* R/W: INT input pin polarity */
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#define IOART_INTAHI 0x00000000 /* active high */
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#define IOART_INTALO 0x00002000 /* active low */
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#define IOART_DELIVS 0x00001000 /* RO: delivery status */
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#define IOART_DESTMOD 0x00000800 /* R/W: destination mode */
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#define IOART_DESTPHY 0x00000000 /* physical */
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#define IOART_DESTLOG 0x00000800 /* logical */
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#define IOART_DELMOD 0x00000700 /* R/W: delivery mode */
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#define IOART_DELFIXED 0x00000000 /* fixed */
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#define IOART_DELLOPRI 0x00000100 /* lowest priority */
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#define IOART_DELSMI 0x00000200 /* System Management INT */
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#define IOART_DELRSV1 0x00000300 /* reserved */
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#define IOART_DELNMI 0x00000400 /* NMI signal */
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#define IOART_DELINIT 0x00000500 /* INIT signal */
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#define IOART_DELRSV2 0x00000600 /* reserved */
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#define IOART_DELEXINT 0x00000700 /* External INTerrupt */
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#define IOART_INTVEC 0x000000ff /* R/W: INTerrupt vector field */
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/* fields in VER */
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#define IOART_VER_VERSION 0x000000ff
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#define IOART_VER_MAXREDIR 0x00ff0000
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#define MAXREDIRSHIFT 16
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6
lapic.c
6
lapic.c
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@ -173,6 +173,12 @@ lapic_disableintr(void)
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lapic_write(LAPIC_TPR, 0xFF);
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}
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void
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lapic_eoi(void)
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{
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lapic_write (LAPIC_EOI, 0);
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}
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int
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cpu(void)
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{
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1
main.c
1
main.c
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@ -45,6 +45,7 @@ main0(void)
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cprintf("\nxV6\n\n");
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pic_init(); // initialize PIC
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ioapic_init();
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kinit(); // physical memory allocator
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tvinit(); // trap vectors
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idtinit(); // CPU's idt
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29
mp.c
29
mp.c
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@ -29,12 +29,12 @@ static char* buses[] = {
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0,
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};
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#define APBOOTCODE 0x7000 // XXX hack
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static struct mp* mp; // The MP floating point structure
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struct cpu cpus[NCPU];
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int ncpu;
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uchar ioapic_id;
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static struct cpu *bcpu;
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static struct mp* mp; // The MP floating point structure
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static struct mp*
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mp_scan(uchar *addr, int len)
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@ -112,7 +112,6 @@ mp_detect(void)
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if(sum || (pcmp->version != 1 && pcmp->version != 4))
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return 3;
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cprintf("Mp spec rev #: %x imcrp 0x%x\n", mp->specrev, mp->imcrp);
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return 0;
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}
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@ -124,12 +123,15 @@ mp_init(void)
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struct mpctb *mpctb;
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struct mppe *proc;
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struct mpbe *bus;
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struct mpioapic *ioapic;
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struct mpie *intr;
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int i;
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uchar byte;
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ncpu = 0;
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if ((r = mp_detect()) != 0) return;
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cprintf ("This computer is a multiprocessor!\n");
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cprintf("Mp spec rev #: %x imcrp 0x%x\n", mp->specrev, mp->imcrp);
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/*
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* Run through the table saving information needed for starting
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@ -164,11 +166,14 @@ mp_init(void)
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p += sizeof(struct mpbe);
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continue;
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case MPIOAPIC:
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cprintf("an I/O APIC\n");
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ioapic = (struct mpioapic *) p;
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cprintf("an I/O APIC: id %d %x\n", ioapic->apicno, ioapic->flags);
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ioapic_id = ioapic->apicno;
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p += sizeof(struct mpioapic);
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continue;
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case MPIOINTR:
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cprintf("an I/O intr\n");
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intr = (struct mpie *) p;
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// cprintf("an I/O intr: type %d flags 0x%x bus %d souce bus irq %d dest ioapic id %d dest ioapic intin %d\n", intr->intr, intr->flags, intr->busno, intr->irq, intr->apicno, intr->intin);
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p += sizeof(struct mpie);
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continue;
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default:
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@ -181,9 +186,17 @@ mp_init(void)
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}
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}
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if (mp->imcrp) { // it appears that bochs doesn't support IMCR, and code won't run
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outb(0x22, 0x70); /* select IMCR */
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byte = inb(0x23); /* current contents */
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byte |= 0x01; /* mask external INTR */
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outb(0x23, byte); /* disconnect 8259s/NMI */
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}
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cprintf("ncpu: %d boot %d\n", ncpu, bcpu-cpus);
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}
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int
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mp_bcpu(void)
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{
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@ -192,6 +205,8 @@ mp_bcpu(void)
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extern void mpmain(void);
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#define APBOOTCODE 0x7000 // XXX hack
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void
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mp_startthem(void)
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{
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1
picirq.c
1
picirq.c
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@ -67,7 +67,6 @@ pic_init(void)
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if (irq_mask_8259A != 0xFFFF)
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irq_setmask_8259A(irq_mask_8259A);
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}
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void
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