ilo-pona/xv6-65oo2
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Apparently the initial interrupt count lapic[TICR]

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must be set *after* initializing the lapic[TIMER] vector.

Doing this, we now get clock interrupts on cpu 1.
(No idea why we always got them on cpu 0.)

Don't write to TCCR - it is read-only.
This commit is contained in:
rsc 2007-09-26 20:34:12 +00:00
parent 355073ea9e
commit d5596cd61d
2 changed files with 3 additions and 10 deletions
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4
defs.h
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@ -70,13 +70,9 @@ void kbd_intr(void);
// lapic.c
int cpu(void);
extern volatile uint* lapic;
void lapic_disableintr(void);
void lapic_enableintr(void);
void lapic_eoi(void);
void lapic_init(int);
void lapic_startap(uchar, uint);
void lapic_timerinit(void);
void lapic_timerintr(void);
// mp.c
extern int ismp;

9
lapic.c
View file

@ -46,14 +46,11 @@ lapic_init(int c)
// The timer repeatedly counts down at bus frequency
// from lapic[TICR] and then issues an interrupt.
// Lapic[TCCR] is the current counter value.
// If xv6 cared more about precise timekeeping, the
// values of TICR and TCCR would be calibrated using
// an external time source.
// If xv6 cared more about precise timekeeping,
// TICR would be calibrated using an external time source.
lapic[TDCR] = X1;
lapic[TICR] = 10000000;
lapic[TCCR] = 10000000;
lapic[TIMER] = PERIODIC | (IRQ_OFFSET + IRQ_TIMER);
lapic[TICR] = 10000000;
// Disable logical interrupt lines.
lapic[LINT0] = MASKED;