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make -O work with asm volatile(...)

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This commit is contained in:
Robert Morris 2019-06-05 15:05:56 -04:00
parent 5684556c19
commit dff7ab3f8f
3 changed files with 35 additions and 35 deletions
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2
Makefile
View file

@ -50,7 +50,7 @@ OBJCOPY = $(TOOLPREFIX)objcopy
OBJDUMP = $(TOOLPREFIX)objdump OBJDUMP = $(TOOLPREFIX)objdump
# CFLAGS = -fno-pic -static -fno-builtin -fno-strict-aliasing -Wall -MD -ggdb -Werror -fno-omit-frame-pointer -O # CFLAGS = -fno-pic -static -fno-builtin -fno-strict-aliasing -Wall -MD -ggdb -Werror -fno-omit-frame-pointer -O
CFLAGS = -Wall -Werror CFLAGS = -Wall -Werror -O
CFLAGS += -mcmodel=medany CFLAGS += -mcmodel=medany
CFLAGS += -ffreestanding -fno-common -nostdlib -mno-relax CFLAGS += -ffreestanding -fno-common -nostdlib -mno-relax
CFLAGS += $(shell $(CC) -fno-stack-protector -E -x c /dev/null >/dev/null 2>&1 && echo -fno-stack-protector) CFLAGS += $(shell $(CC) -fno-stack-protector -E -x c /dev/null >/dev/null 2>&1 && echo -fno-stack-protector)

66
riscv.h
View file

@ -3,7 +3,7 @@ static inline uint64
r_mhartid() r_mhartid()
{ {
uint64 x; uint64 x;
asm("csrr %0, mhartid" : "=r" (x) ); asm volatile("csrr %0, mhartid" : "=r" (x) );
return x; return x;
} }
@ -19,14 +19,14 @@ static inline uint64
r_mstatus() r_mstatus()
{ {
uint64 x; uint64 x;
asm("csrr %0, mstatus" : "=r" (x) ); asm volatile("csrr %0, mstatus" : "=r" (x) );
return x; return x;
} }
static inline void static inline void
w_mstatus(uint64 x) w_mstatus(uint64 x)
{ {
asm("csrw mstatus, %0" : : "r" (x)); asm volatile("csrw mstatus, %0" : : "r" (x));
} }
// machine exception program counter, holds the // machine exception program counter, holds the
@ -35,7 +35,7 @@ w_mstatus(uint64 x)
static inline void static inline void
w_mepc(uint64 x) w_mepc(uint64 x)
{ {
asm("csrw mepc, %0" : : "r" (x)); asm volatile("csrw mepc, %0" : : "r" (x));
} }
// Supervisor Status Register, sstatus // Supervisor Status Register, sstatus
@ -50,14 +50,14 @@ static inline uint64
r_sstatus() r_sstatus()
{ {
uint64 x; uint64 x;
asm("csrr %0, sstatus" : "=r" (x) ); asm volatile("csrr %0, sstatus" : "=r" (x) );
return x; return x;
} }
static inline void static inline void
w_sstatus(uint64 x) w_sstatus(uint64 x)
{ {
asm("csrw sstatus, %0" : : "r" (x)); asm volatile("csrw sstatus, %0" : : "r" (x));
} }
// Supervisor Interrupt Pending // Supervisor Interrupt Pending
@ -65,14 +65,14 @@ static inline uint64
r_sip() r_sip()
{ {
uint64 x; uint64 x;
asm("csrr %0, sip" : "=r" (x) ); asm volatile("csrr %0, sip" : "=r" (x) );
return x; return x;
} }
static inline void static inline void
w_sip(uint64 x) w_sip(uint64 x)
{ {
asm("csrw sip, %0" : : "r" (x)); asm volatile("csrw sip, %0" : : "r" (x));
} }
// Supervisor Interrupt Enable // Supervisor Interrupt Enable
@ -83,14 +83,14 @@ static inline uint64
r_sie() r_sie()
{ {
uint64 x; uint64 x;
asm("csrr %0, sie" : "=r" (x) ); asm volatile("csrr %0, sie" : "=r" (x) );
return x; return x;
} }
static inline void static inline void
w_sie(uint64 x) w_sie(uint64 x)
{ {
asm("csrw sie, %0" : : "r" (x)); asm volatile("csrw sie, %0" : : "r" (x));
} }
// Machine-mode Interrupt Enable // Machine-mode Interrupt Enable
@ -101,14 +101,14 @@ static inline uint64
r_mie() r_mie()
{ {
uint64 x; uint64 x;
asm("csrr %0, mie" : "=r" (x) ); asm volatile("csrr %0, mie" : "=r" (x) );
return x; return x;
} }
static inline void static inline void
w_mie(uint64 x) w_mie(uint64 x)
{ {
asm("csrw mie, %0" : : "r" (x)); asm volatile("csrw mie, %0" : : "r" (x));
} }
// machine exception program counter, holds the // machine exception program counter, holds the
@ -117,14 +117,14 @@ w_mie(uint64 x)
static inline void static inline void
w_sepc(uint64 x) w_sepc(uint64 x)
{ {
asm("csrw sepc, %0" : : "r" (x)); asm volatile("csrw sepc, %0" : : "r" (x));
} }
static inline uint64 static inline uint64
r_sepc() r_sepc()
{ {
uint64 x; uint64 x;
asm("csrr %0, sepc" : "=r" (x) ); asm volatile("csrr %0, sepc" : "=r" (x) );
return x; return x;
} }
@ -133,14 +133,14 @@ static inline uint64
r_medeleg() r_medeleg()
{ {
uint64 x; uint64 x;
asm("csrr %0, medeleg" : "=r" (x) ); asm volatile("csrr %0, medeleg" : "=r" (x) );
return x; return x;
} }
static inline void static inline void
w_medeleg(uint64 x) w_medeleg(uint64 x)
{ {
asm("csrw medeleg, %0" : : "r" (x)); asm volatile("csrw medeleg, %0" : : "r" (x));
} }
// Machine Interrupt Delegation // Machine Interrupt Delegation
@ -148,14 +148,14 @@ static inline uint64
r_mideleg() r_mideleg()
{ {
uint64 x; uint64 x;
asm("csrr %0, mideleg" : "=r" (x) ); asm volatile("csrr %0, mideleg" : "=r" (x) );
return x; return x;
} }
static inline void static inline void
w_mideleg(uint64 x) w_mideleg(uint64 x)
{ {
asm("csrw mideleg, %0" : : "r" (x)); asm volatile("csrw mideleg, %0" : : "r" (x));
} }
// Supervisor Trap-Vector Base Address // Supervisor Trap-Vector Base Address
@ -163,14 +163,14 @@ w_mideleg(uint64 x)
static inline void static inline void
w_stvec(uint64 x) w_stvec(uint64 x)
{ {
asm("csrw stvec, %0" : : "r" (x)); asm volatile("csrw stvec, %0" : : "r" (x));
} }
static inline uint64 static inline uint64
r_stvec() r_stvec()
{ {
uint64 x; uint64 x;
asm("csrr %0, stvec" : "=r" (x) ); asm volatile("csrr %0, stvec" : "=r" (x) );
return x; return x;
} }
@ -178,7 +178,7 @@ r_stvec()
static inline void static inline void
w_mtvec(uint64 x) w_mtvec(uint64 x)
{ {
asm("csrw mtvec, %0" : : "r" (x)); asm volatile("csrw mtvec, %0" : : "r" (x));
} }
// use riscv's sv39 page table scheme. // use riscv's sv39 page table scheme.
@ -191,14 +191,14 @@ w_mtvec(uint64 x)
static inline void static inline void
w_satp(uint64 x) w_satp(uint64 x)
{ {
asm("csrw satp, %0" : : "r" (x)); asm volatile("csrw satp, %0" : : "r" (x));
} }
static inline uint64 static inline uint64
r_satp() r_satp()
{ {
uint64 x; uint64 x;
asm("csrr %0, satp" : "=r" (x) ); asm volatile("csrr %0, satp" : "=r" (x) );
return x; return x;
} }
@ -206,13 +206,13 @@ r_satp()
static inline void static inline void
w_sscratch(uint64 x) w_sscratch(uint64 x)
{ {
asm("csrw sscratch, %0" : : "r" (x)); asm volatile("csrw sscratch, %0" : : "r" (x));
} }
static inline void static inline void
w_mscratch(uint64 x) w_mscratch(uint64 x)
{ {
asm("csrw mscratch, %0" : : "r" (x)); asm volatile("csrw mscratch, %0" : : "r" (x));
} }
// Supervisor Trap Cause // Supervisor Trap Cause
@ -220,7 +220,7 @@ static inline uint64
r_scause() r_scause()
{ {
uint64 x; uint64 x;
asm("csrr %0, scause" : "=r" (x) ); asm volatile("csrr %0, scause" : "=r" (x) );
return x; return x;
} }
@ -229,7 +229,7 @@ static inline uint64
r_stval() r_stval()
{ {
uint64 x; uint64 x;
asm("csrr %0, stval" : "=r" (x) ); asm volatile("csrr %0, stval" : "=r" (x) );
return x; return x;
} }
@ -237,14 +237,14 @@ r_stval()
static inline void static inline void
w_mcounteren(uint64 x) w_mcounteren(uint64 x)
{ {
asm("csrw mcounteren, %0" : : "r" (x)); asm volatile("csrw mcounteren, %0" : : "r" (x));
} }
static inline uint64 static inline uint64
r_mcounteren() r_mcounteren()
{ {
uint64 x; uint64 x;
asm("csrr %0, mcounteren" : "=r" (x) ); asm volatile("csrr %0, mcounteren" : "=r" (x) );
return x; return x;
} }
@ -253,7 +253,7 @@ static inline uint64
r_time() r_time()
{ {
uint64 x; uint64 x;
asm("csrr %0, time" : "=r" (x) ); asm volatile("csrr %0, time" : "=r" (x) );
return x; return x;
} }
@ -284,7 +284,7 @@ static inline uint64
r_sp() r_sp()
{ {
uint64 x; uint64 x;
asm("mv %0, sp" : "=r" (x) ); asm volatile("mv %0, sp" : "=r" (x) );
return x; return x;
} }
@ -294,14 +294,14 @@ static inline uint64
r_tp() r_tp()
{ {
uint64 x; uint64 x;
asm("mv %0, tp" : "=r" (x) ); asm volatile("mv %0, tp" : "=r" (x) );
return x; return x;
} }
static inline void static inline void
w_tp(uint64 x) w_tp(uint64 x)
{ {
asm("mv tp, %0" : : "r" (x)); asm volatile("mv tp, %0" : : "r" (x));
} }
#define PGSIZE 4096 // bytes per page #define PGSIZE 4096 // bytes per page

2
start.c
View file

@ -52,5 +52,5 @@ mstart()
w_tp(id); w_tp(id);
// call main() in supervisor mode. // call main() in supervisor mode.
asm("mret"); asm volatile("mret");
} }