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This commit is contained in:
Robert Morris 2019-06-03 14:16:51 -04:00
parent a9c1a6f742
commit e630e0743b
1 changed files with 13 additions and 11 deletions
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24
trap.c
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@ -21,6 +21,19 @@ trapinit(void)
// send interrupts and exceptions to kerneltrap(). // send interrupts and exceptions to kerneltrap().
w_stvec((uint64)kerneltrap); w_stvec((uint64)kerneltrap);
// set up the riscv Platform Level Interrupt Controller
// to send uart interrupts to hart 0 S-Mode.
// qemu makes UART0 be interrupt number 10.
int irq = 10;
// set uart's priority to be non-zero (otherwise disabled).
*(uint*)(0x0c000000L + irq*4) = 1;
// set uart's enable bit for hart 0 S-mode.
*(uint*)0x0c002080 = (1 << irq);
// set hart 0 S-mode priority threshold to 0.
*(uint*)0x0c201000 = 0;
initlock(&tickslock, "time"); initlock(&tickslock, "time");
} }
@ -43,17 +56,6 @@ usertrap(void)
// save user program counter. // save user program counter.
p->tf->epc = r_sepc(); p->tf->epc = r_sepc();
// PLIC setup
// qemu makes UART0 be interrupt number 10.
int irq = 10;
// set uart's priority to be non-zero (otherwise disabled).
*(uint*)(0x0c000000L + irq*4) = 1;
// set uart's enable bit for hart 0 s-mode.
*(uint*)0x0c002080 = (1 << irq);
// hart 0 S-mode priority threshold.
*(uint*)0x0c201000 = 0;
intr_on(); intr_on();
if(r_scause() == 8){ if(r_scause() == 8){