214 lines
3.5 KiB
C
214 lines
3.5 KiB
C
// Routines to let C code use special x86 instructions.
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static inline uchar
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inb(ushort port)
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{
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uchar data;
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asm volatile("in %1,%0" : "=a" (data) : "d" (port));
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return data;
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}
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static inline void
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insl(int port, void *addr, int cnt)
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{
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asm volatile("cld; rep insl" :
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"=D" (addr), "=c" (cnt) :
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"d" (port), "0" (addr), "1" (cnt) :
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"memory", "cc");
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}
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static inline void
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outb(ushort port, uchar data)
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{
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asm volatile("out %0,%1" : : "a" (data), "d" (port));
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}
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static inline void
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outw(ushort port, ushort data)
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{
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asm volatile("out %0,%1" : : "a" (data), "d" (port));
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}
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static inline void
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outsl(int port, const void *addr, int cnt)
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{
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asm volatile("cld; rep outsl" :
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"=S" (addr), "=c" (cnt) :
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"d" (port), "0" (addr), "1" (cnt) :
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"cc");
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}
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static inline void
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stosb(void *addr, int data, int cnt)
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{
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asm volatile("cld; rep stosb" :
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"=D" (addr), "=c" (cnt) :
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"0" (addr), "1" (cnt), "a" (data) :
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"memory", "cc");
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}
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struct segdesc;
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static inline void
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lgdt(struct segdesc *p, int size)
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{
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volatile ushort pd[3];
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pd[0] = size-1;
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pd[1] = (uint)p;
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pd[2] = (uint)p >> 16;
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asm volatile("lgdt (%0)" : : "r" (pd));
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}
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struct gatedesc;
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static inline void
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lidt(struct gatedesc *p, int size)
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{
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volatile ushort pd[3];
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pd[0] = size-1;
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pd[1] = (uint)p;
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pd[2] = (uint)p >> 16;
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asm volatile("lidt (%0)" : : "r" (pd));
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}
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static inline void
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ltr(ushort sel)
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{
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asm volatile("ltr %0" : : "r" (sel));
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}
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static inline uint
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readeflags(void)
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{
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uint eflags;
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asm volatile("pushfl; popl %0" : "=r" (eflags));
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return eflags;
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}
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static inline void
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loadgs(ushort v)
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{
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asm volatile("movw %0, %%gs" : : "r" (v));
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}
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static inline uint
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rebp(void)
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{
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uint val;
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asm volatile("movl %%ebp,%0" : "=r" (val));
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return val;
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}
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static inline uint
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resp(void)
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{
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uint val;
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asm volatile("movl %%esp,%0" : "=r" (val));
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return val;
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}
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static inline void
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cli(void)
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{
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asm volatile("cli");
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}
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static inline void
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sti(void)
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{
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asm volatile("sti");
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}
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static inline uint
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xchg(volatile uint *addr, uint newval)
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{
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uint result;
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// The + in "+m" denotes a read-modify-write operand.
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asm volatile("lock; xchgl %0, %1" :
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"+m" (*addr), "=a" (result) :
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"1" (newval) :
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"cc");
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return result;
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}
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//PAGEBREAK!
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static inline void
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lcr0(uint val)
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{
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asm volatile("movl %0,%%cr0" : : "r" (val));
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}
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static inline uint
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rcr0(void)
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{
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uint val;
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asm volatile("movl %%cr0,%0" : "=r" (val));
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return val;
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}
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static inline uint
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rcr2(void)
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{
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uint val;
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asm volatile("movl %%cr2,%0" : "=r" (val));
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return val;
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}
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static inline void
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lcr3(uint val)
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{
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asm volatile("movl %0,%%cr3" : : "r" (val));
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}
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static inline uint
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rcr3(void)
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{
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uint val;
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asm volatile("movl %%cr3,%0" : "=r" (val));
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return val;
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}
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//PAGEBREAK: 36
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// Layout of the trap frame built on the stack by the
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// hardware and by trapasm.S, and passed to trap().
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struct trapframe {
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// registers as pushed by pusha
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uint edi;
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uint esi;
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uint ebp;
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uint oesp; // useless & ignored
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uint ebx;
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uint edx;
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uint ecx;
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uint eax;
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// rest of trap frame
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ushort gs;
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ushort padding1;
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ushort fs;
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ushort padding2;
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ushort es;
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ushort padding3;
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ushort ds;
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ushort padding4;
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uint trapno;
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// below here defined by x86 hardware
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uint err;
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uint eip;
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ushort cs;
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ushort padding5;
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uint eflags;
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// below here only when crossing rings, such as from user to kernel
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uint esp;
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ushort ss;
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ushort padding6;
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};
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