f70172129c
if no lapic available, use 8253pit for clock now xv6 runs both on qemu (uniprocessor) and bochs (uniprocessor and MP)
182 lines
3.2 KiB
C
182 lines
3.2 KiB
C
// Simple PIO-based (non-DMA) IDE driver code.
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#include "types.h"
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#include "param.h"
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#include "mmu.h"
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#include "proc.h"
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#include "defs.h"
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#include "x86.h"
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#include "traps.h"
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#include "spinlock.h"
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#define IDE_BSY 0x80
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#define IDE_DRDY 0x40
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#define IDE_DF 0x20
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#define IDE_ERR 0x01
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#define IDE_CMD_READ 0x20
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#define IDE_CMD_WRITE 0x30
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struct ide_request {
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int diskno;
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uint secno;
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void *addr;
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uint nsecs;
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uint read;
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};
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struct ide_request request[NREQUEST];
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int head, tail;
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struct spinlock ide_lock;
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int disk_1_present;
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int disk_channel;
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int ide_probe_disk1(void);
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static int
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ide_wait_ready(int check_error)
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{
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int r;
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while(((r = inb(0x1F7)) & (IDE_BSY|IDE_DRDY)) != IDE_DRDY)
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;
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if(check_error && (r & (IDE_DF|IDE_ERR)) != 0)
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return -1;
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return 0;
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}
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void
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ide_init(void)
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{
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initlock(&ide_lock, "ide");
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irq_setmask_8259A(irq_mask_8259A & ~(1 << IRQ_IDE));
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ioapic_enable (IRQ_IDE, ncpu - 1);
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ide_wait_ready(0);
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disk_1_present = ide_probe_disk1();
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}
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void
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ide_intr(void)
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{
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acquire(&ide_lock);
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wakeup(&request[tail]);
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release(&ide_lock);
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}
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int
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ide_probe_disk1(void)
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{
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int r, x;
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// wait for Device 0 to be ready
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ide_wait_ready(0);
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// switch to Device 1
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outb(0x1F6, 0xE0 | (1<<4));
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// check for Device 1 to be ready for a while
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for(x = 0; x < 1000 && (r = inb(0x1F7)) == 0; x++)
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;
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// switch back to Device 0
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outb(0x1F6, 0xE0 | (0<<4));
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return x < 1000;
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}
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void
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ide_start_request (void)
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{
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struct ide_request *r;
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if(head != tail) {
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r = &request[tail];
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ide_wait_ready(0);
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outb(0x3f6, 0); // generate interrupt
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outb(0x1F2, r->nsecs);
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outb(0x1F3, r->secno & 0xFF);
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outb(0x1F4, (r->secno >> 8) & 0xFF);
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outb(0x1F5, (r->secno >> 16) & 0xFF);
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outb(0x1F6, 0xE0 | ((r->diskno&1)<<4) | ((r->secno>>24)&0x0F));
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if(r->read)
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outb(0x1F7, IDE_CMD_READ);
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else {
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outb(0x1F7, IDE_CMD_WRITE);
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outsl(0x1F0, r->addr, 512/4);
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}
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}
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}
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void*
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ide_start_rw(int diskno, uint secno, void *addr, uint nsecs, int read)
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{
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struct ide_request *r;
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if(diskno && !disk_1_present)
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panic("ide disk 1 not present");
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while((head + 1) % NREQUEST == tail)
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sleep(&disk_channel, &ide_lock);
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r = &request[head];
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r->secno = secno;
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r->addr = addr;
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r->nsecs = nsecs;
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r->diskno = diskno;
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r->read = read;
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head = (head + 1) % NREQUEST;
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ide_start_request();
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return r;
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}
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int
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ide_finish(void *c)
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{
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int r;
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struct ide_request *req = (struct ide_request*) c;
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if(req->read) {
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if((r = ide_wait_ready(1)) >= 0)
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insl(0x1F0, req->addr, 512/4);
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}
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if((head + 1) % NREQUEST == tail) {
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wakeup(&disk_channel);
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}
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tail = (tail + 1) % NREQUEST;
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ide_start_request();
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return 0;
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}
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int
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ide_write(int diskno, uint secno, const void *src, uint nsecs)
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{
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int r;
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if(nsecs > 256)
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panic("ide_write");
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ide_wait_ready(0);
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outb(0x1F2, nsecs);
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outb(0x1F3, secno & 0xFF);
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outb(0x1F4, (secno >> 8) & 0xFF);
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outb(0x1F5, (secno >> 16) & 0xFF);
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outb(0x1F6, 0xE0 | ((diskno&1)<<4) | ((secno>>24)&0x0F));
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outb(0x1F7, 0x30); // CMD 0x30 means write sector
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for(; nsecs > 0; nsecs--, src += 512) {
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if((r = ide_wait_ready(1)) < 0)
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return r;
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outsl(0x1F0, src, 512/4);
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}
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return 0;
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}
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