224 lines
8.4 KiB
C
224 lines
8.4 KiB
C
// This file contains definitions for the
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// x86 memory management unit (MMU).
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// Eflags register
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#define FL_CF 0x00000001 // Carry Flag
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#define FL_PF 0x00000004 // Parity Flag
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#define FL_AF 0x00000010 // Auxiliary carry Flag
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#define FL_ZF 0x00000040 // Zero Flag
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#define FL_SF 0x00000080 // Sign Flag
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#define FL_TF 0x00000100 // Trap Flag
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#define FL_IF 0x00000200 // Interrupt Enable
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#define FL_DF 0x00000400 // Direction Flag
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#define FL_OF 0x00000800 // Overflow Flag
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#define FL_IOPL_MASK 0x00003000 // I/O Privilege Level bitmask
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#define FL_IOPL_0 0x00000000 // IOPL == 0
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#define FL_IOPL_1 0x00001000 // IOPL == 1
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#define FL_IOPL_2 0x00002000 // IOPL == 2
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#define FL_IOPL_3 0x00003000 // IOPL == 3
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#define FL_NT 0x00004000 // Nested Task
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#define FL_RF 0x00010000 // Resume Flag
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#define FL_VM 0x00020000 // Virtual 8086 mode
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#define FL_AC 0x00040000 // Alignment Check
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#define FL_VIF 0x00080000 // Virtual Interrupt Flag
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#define FL_VIP 0x00100000 // Virtual Interrupt Pending
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#define FL_ID 0x00200000 // ID flag
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// Segment Descriptor
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struct segdesc {
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uint lim_15_0 : 16; // Low bits of segment limit
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uint base_15_0 : 16; // Low bits of segment base address
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uint base_23_16 : 8; // Middle bits of segment base address
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uint type : 4; // Segment type (see STS_ constants)
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uint s : 1; // 0 = system, 1 = application
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uint dpl : 2; // Descriptor Privilege Level
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uint p : 1; // Present
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uint lim_19_16 : 4; // High bits of segment limit
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uint avl : 1; // Unused (available for software use)
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uint rsv1 : 1; // Reserved
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uint db : 1; // 0 = 16-bit segment, 1 = 32-bit segment
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uint g : 1; // Granularity: limit scaled by 4K when set
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uint base_31_24 : 8; // High bits of segment base address
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};
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// Normal segment
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#define SEG(type, base, lim, dpl) (struct segdesc) \
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{ ((lim) >> 12) & 0xffff, (uint)(base) & 0xffff, \
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((uint)(base) >> 16) & 0xff, type, 1, dpl, 1, \
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(uint)(lim) >> 28, 0, 0, 1, 1, (uint)(base) >> 24 }
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#define SEG16(type, base, lim, dpl) (struct segdesc) \
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{ (lim) & 0xffff, (uint)(base) & 0xffff, \
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((uint)(base) >> 16) & 0xff, type, 1, dpl, 1, \
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(uint)(lim) >> 16, 0, 0, 1, 0, (uint)(base) >> 24 }
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#define DPL_USER 0x3 // User DPL
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// Application segment type bits
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#define STA_X 0x8 // Executable segment
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#define STA_E 0x4 // Expand down (non-executable segments)
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#define STA_C 0x4 // Conforming code segment (executable only)
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#define STA_W 0x2 // Writeable (non-executable segments)
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#define STA_R 0x2 // Readable (executable segments)
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#define STA_A 0x1 // Accessed
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//
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// System segment type bits
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#define STS_T16A 0x1 // Available 16-bit TSS
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#define STS_LDT 0x2 // Local Descriptor Table
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#define STS_T16B 0x3 // Busy 16-bit TSS
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#define STS_CG16 0x4 // 16-bit Call Gate
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#define STS_TG 0x5 // Task Gate / Coum Transmitions
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#define STS_IG16 0x6 // 16-bit Interrupt Gate
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#define STS_TG16 0x7 // 16-bit Trap Gate
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#define STS_T32A 0x9 // Available 32-bit TSS
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#define STS_T32B 0xB // Busy 32-bit TSS
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#define STS_CG32 0xC // 32-bit Call Gate
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#define STS_IG32 0xE // 32-bit Interrupt Gate
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#define STS_TG32 0xF // 32-bit Trap Gate
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// A linear address 'la' has a three-part structure as follows:
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//
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// +--------10------+-------10-------+---------12----------+
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// | Page Directory | Page Table | Offset within Page |
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// | Index | Index | |
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// +----------------+----------------+---------------------+
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// \--- PDX(la) --/ \--- PTX(la) --/
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// page directory index
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#define PDX(la) ((((uint) (la)) >> PDXSHIFT) & 0x3FF)
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// page table index
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#define PTX(la) ((((uint) (la)) >> PTXSHIFT) & 0x3FF)
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// construct linear address from indexes and offset
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#define PGADDR(d, t, o) ((uint) ((d) << PDXSHIFT | (t) << PTXSHIFT | (o)))
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// turn a kernel linear address into a physical address.
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// all of the kernel data structures have linear and
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// physical addresses that are equal.
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#define PADDR(a) ((uint) a)
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// Page directory and page table constants.
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#define NPDENTRIES 1024 // page directory entries per page directory
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#define NPTENTRIES 1024 // page table entries per page table
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#define PGSIZE 4096 // bytes mapped by a page
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#define PGSHIFT 12 // log2(PGSIZE)
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#define PTXSHIFT 12 // offset of PTX in a linear address
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#define PDXSHIFT 22 // offset of PDX in a linear address
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#define PGROUNDUP(sz) (((sz)+PGSIZE-1) & ~(PGSIZE-1))
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#define PGROUNDDOWN(a) ((char*)((((unsigned int)a) & ~(PGSIZE-1))))
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// Page table/directory entry flags.
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#define PTE_P 0x001 // Present
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#define PTE_W 0x002 // Writeable
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#define PTE_U 0x004 // User
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#define PTE_PWT 0x008 // Write-Through
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#define PTE_PCD 0x010 // Cache-Disable
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#define PTE_A 0x020 // Accessed
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#define PTE_D 0x040 // Dirty
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#define PTE_PS 0x080 // Page Size
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#define PTE_MBZ 0x180 // Bits must be zero
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// Address in page table or page directory entry
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#define PTE_ADDR(pte) ((uint) (pte) & ~0xFFF)
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typedef uint pte_t;
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// Control Register flags
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#define CR0_PE 0x00000001 // Protection Enable
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#define CR0_MP 0x00000002 // Monitor coProcessor
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#define CR0_EM 0x00000004 // Emulation
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#define CR0_TS 0x00000008 // Task Switched
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#define CR0_ET 0x00000010 // Extension Type
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#define CR0_NE 0x00000020 // Numeric Errror
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#define CR0_WP 0x00010000 // Write Protect
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#define CR0_AM 0x00040000 // Alignment Mask
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#define CR0_NW 0x20000000 // Not Writethrough
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#define CR0_CD 0x40000000 // Cache Disable
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#define CR0_PG 0x80000000 // Paging
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// PAGEBREAK: 40
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// Task state segment format
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struct taskstate {
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uint link; // Old ts selector
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uint esp0; // Stack pointers and segment selectors
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ushort ss0; // after an increase in privilege level
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ushort padding1;
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uint *esp1;
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ushort ss1;
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ushort padding2;
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uint *esp2;
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ushort ss2;
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ushort padding3;
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void *cr3; // Page directory base
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uint *eip; // Saved state from last task switch
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uint eflags;
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uint eax; // More saved state (registers)
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uint ecx;
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uint edx;
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uint ebx;
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uint *esp;
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uint *ebp;
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uint esi;
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uint edi;
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ushort es; // Even more saved state (segment selectors)
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ushort padding4;
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ushort cs;
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ushort padding5;
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ushort ss;
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ushort padding6;
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ushort ds;
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ushort padding7;
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ushort fs;
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ushort padding8;
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ushort gs;
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ushort padding9;
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ushort ldt;
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ushort padding10;
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ushort t; // Trap on task switch
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ushort iomb; // I/O map base address
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};
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// PAGEBREAK: 12
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// Gate descriptors for interrupts and traps
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struct gatedesc {
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uint off_15_0 : 16; // low 16 bits of offset in segment
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uint cs : 16; // code segment selector
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uint args : 5; // # args, 0 for interrupt/trap gates
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uint rsv1 : 3; // reserved(should be zero I guess)
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uint type : 4; // type(STS_{TG,IG32,TG32})
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uint s : 1; // must be 0 (system)
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uint dpl : 2; // descriptor(meaning new) privilege level
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uint p : 1; // Present
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uint off_31_16 : 16; // high bits of offset in segment
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};
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// Set up a normal interrupt/trap gate descriptor.
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// - istrap: 1 for a trap (= exception) gate, 0 for an interrupt gate.
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// interrupt gate clears FL_IF, trap gate leaves FL_IF alone
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// - sel: Code segment selector for interrupt/trap handler
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// - off: Offset in code segment for interrupt/trap handler
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// - dpl: Descriptor Privilege Level -
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// the privilege level required for software to invoke
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// this interrupt/trap gate explicitly using an int instruction.
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#define SETGATE(gate, istrap, sel, off, d) \
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{ \
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(gate).off_15_0 = (uint) (off) & 0xffff; \
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(gate).cs = (sel); \
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(gate).args = 0; \
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(gate).rsv1 = 0; \
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(gate).type = (istrap) ? STS_TG32 : STS_IG32; \
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(gate).s = 0; \
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(gate).dpl = (d); \
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(gate).p = 1; \
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(gate).off_31_16 = (uint) (off) >> 16; \
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}
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