173 lines
3.4 KiB
C
173 lines
3.4 KiB
C
// Machine Status Register, mstatus
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#define MSTATUS_MPP_MASK (3L << 11)
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#define MSTATUS_MPP_M (3L << 11)
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#define MSTATUS_MPP_S (1L << 11)
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#define MSTATUS_MPP_U (0L << 11)
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static inline uint64
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r_mstatus()
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{
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uint64 x;
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asm("csrr %0, mstatus" : "=r" (x) );
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return x;
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}
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static inline void
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w_mstatus(uint64 x)
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{
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asm("csrw mstatus, %0" : : "r" (x));
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}
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// machine exception program counter, holds the
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// instruction address to which a return from
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// exception will go.
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static inline void
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w_mepc(uint64 x)
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{
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asm("csrw mepc, %0" : : "r" (x));
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}
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// Supervisor Status Register, sstatus
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#define SSTATUS_SPP (1L << 8) // 1=Supervisor, 0=User
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static inline uint64
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r_sstatus()
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{
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uint64 x;
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asm("csrr %0, sstatus" : "=r" (x) );
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return x;
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}
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static inline void
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w_sstatus(uint64 x)
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{
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asm("csrw sstatus, %0" : : "r" (x));
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}
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// machine exception program counter, holds the
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// instruction address to which a return from
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// exception will go.
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static inline void
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w_sepc(uint64 x)
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{
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asm("csrw sepc, %0" : : "r" (x));
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}
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static inline uint64
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r_sepc()
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{
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uint64 x;
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asm("csrr %0, sepc" : "=r" (x) );
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return x;
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}
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// Machine Exception Delegation
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static inline uint64
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r_medeleg()
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{
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uint64 x;
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asm("csrr %0, medeleg" : "=r" (x) );
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return x;
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}
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static inline void
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w_medeleg(uint64 x)
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{
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asm("csrw medeleg, %0" : : "r" (x));
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}
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// Machine Interrupt Delegation
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static inline uint64
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r_mideleg()
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{
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uint64 x;
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asm("csrr %0, mideleg" : "=r" (x) );
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return x;
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}
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static inline void
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w_mideleg(uint64 x)
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{
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asm("csrw mideleg, %0" : : "r" (x));
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}
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// Supervisor Trap-Vector Base Address
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// low two bits are mode.
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static inline void
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w_stvec(uint64 x)
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{
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asm("csrw stvec, %0" : : "r" (x));
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}
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// use riscv's sv39 page table scheme.
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#define SATP_SV39 (8L << 60)
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#define MAKE_SATP(pagetable) (SATP_SV39 | (((uint64)pagetable) >> 12))
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// supervisor address translation and protection;
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// holds the address of the page table.
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static inline void
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w_satp(uint64 x)
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{
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asm("csrw satp, %0" : : "r" (x));
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}
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static inline uint64
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r_satp()
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{
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uint64 x;
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asm("csrr %0, satp" : "=r" (x) );
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return x;
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}
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// Supervisor Scratch register, for early trap handler in trampoline.S.
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static inline void
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w_sscratch(uint64 x)
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{
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asm("csrw sscratch, %0" : : "r" (x));
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}
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// Supervisor trap cause
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static inline uint64
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r_scause()
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{
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uint64 x;
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asm("csrr %0, scause" : "=r" (x) );
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return x;
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}
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#define PGSIZE 4096 // bytes per page
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#define PGSHIFT 12 // bits of offset within a page
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#define PGROUNDUP(sz) (((sz)+PGSIZE-1) & ~(PGSIZE-1))
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#define PGROUNDDOWN(a) (((a)) & ~(PGSIZE-1))
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#define PTE_V (1L << 0) // valid
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#define PTE_R (1L << 1)
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#define PTE_W (1L << 2)
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#define PTE_X (1L << 3)
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#define PTE_U (1L << 4) // 1 -> user can access
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// shift a physical address to the right place for a PTE.
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#define PA2PTE(pa) ((((uint64)pa) >> 12) << 10)
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#define PTE2PA(pte) (((pte) >> 10) << 12)
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#define PTE_FLAGS(pte) ((pte) & (PTE_V|PTE_R|PTE_W|PTE_X|PTE_U))
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// extract the three 9-bit page table indices from a virtual address.
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#define PXMASK 0x1FF // 9 bits
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#define PXSHIFT(level) (PGSHIFT+(9*(level)))
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#define PX(level, va) ((((uint64) (va)) >> PXSHIFT(level)) & PXMASK)
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// one beyond the highest possible virtual address.
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// MAXVA is actually one bit less than the max allowed by
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// Sv39, to avoid having to sign-extend virtual addresses
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// that have the high bit set.
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#define MAXVA (1L << (9 + 9 + 9 + 12 - 1))
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typedef uint64 pte_t;
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typedef uint64 *pagetable_t; // 512 PTEs
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