ab0db651af
The x86-64 doesn't just add two levels to page tables to support 64 bit addresses, but is a different processor. For example, calling conventions, system calls, and segmentation are different from 32-bit x86. Segmentation is basically gone, but gs/fs in combination with MSRs can be used to hold a per-core pointer. In general, x86-64 is more straightforward than 32-bit x86. The port uses code from sv6 and the xv6 "rsc-amd64" branch. A summary of the changes is as follows: - Booting: switch to grub instead of xv6's bootloader (pass -kernel to qemu), because xv6's boot loader doesn't understand 64bit ELF files. And, we don't care anymore about booting. - Makefile: use -m64 instead of -m32 flag for gcc, delete boot loader, xv6.img, bochs, and memfs. For now dont' use -O2, since usertests with -O2 is bigger than MAXFILE! - Update gdb.tmpl to be for i386 or x86-64 - Console/printf: use stdarg.h and treat 64-bit addresses different from ints (32-bit) - Update elfhdr to be 64 bit - entry.S/entryother.S: add code to switch to 64-bit mode: build a simple page table in 32-bit mode before switching to 64-bit mode, share code for entering boot processor and APs, and tweak boot gdt. The boot gdt is the gdt that the kernel proper also uses. (In 64-bit mode, the gdt/segmentation and task state mostly disappear.) - exec.c: fix passing argv (64-bit now instead of 32-bit). - initcode.c: use syscall instead of int. - kernel.ld: load kernel very high, in top terabyte. 64 bits is a lot of address space! - proc.c: initial return is through new syscall path instead of trapret. - proc.h: update struct cpu to have some scratch space since syscall saves less state than int, update struct context to reflect x86-64 calling conventions. - swtch: simplify for x86-64 calling conventions. - syscall: add fetcharg to handle x86-64 calling convetions (6 arguments are passed through registers), and fetchaddr to read a 64-bit value from user space. - sysfile: update to handle pointers from user space (e.g., sys_exec), which are 64 bits. - trap.c: no special trap vector for sys calls, because x86-64 has a different plan for system calls. - trapasm: one plan for syscalls and one plan for traps (interrupt and exceptions). On x86-64, the kernel is responsible for switching user/kernel stacks. To do, xv6 keeps some scratch space in the cpu structure, and uses MSR GS_KERN_BASE to point to the core's cpu structure (using swapgs). - types.h: add uint64, and change pde_t to uint64 - usertests: exit() when fork fails, which helped in tracking down one of the bugs in the switch from 32-bit to 64-bit - vectors: update to make them 64 bits - vm.c: use bootgdt in kernel too, program MSRs for syscalls and core-local state (for swapgs), walk 4 levels in walkpgdir, add DEVSPACETOP, use task segment to set kernel stack for interrupts (but simpler than in 32-bit mode), add an extra argument to freevm (size of user part of address space) to avoid checking all entries till KERNBASE (there are MANY TB before the top 1TB). - x86: update trapframe to have 64-bit entries, which is what the processor pushes on syscalls and traps. simplify lgdt and lidt, using struct desctr, which needs the gcc directives packed and aligned. TODO: - use int32 instead of int? - simplify curproc(). xv6 has per-cpu state again, but this time it must have it. - avoid repetition in walkpgdir - fix validateint() in usertests.c - fix bugs (e.g., observed one a case of entering kernel with invalid gs or proc
140 lines
3.1 KiB
C
140 lines
3.1 KiB
C
// Multiprocessor support
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// Search memory for MP description structures.
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// http://developer.intel.com/design/pentium/datashts/24201606.pdf
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#include "types.h"
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#include "defs.h"
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#include "param.h"
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#include "memlayout.h"
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#include "mp.h"
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#include "x86.h"
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#include "mmu.h"
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#include "proc.h"
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struct cpu cpus[NCPU];
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int ncpu;
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uchar ioapicid;
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static uchar
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sum(uchar *addr, int len)
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{
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int i, sum;
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sum = 0;
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for(i=0; i<len; i++)
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sum += addr[i];
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return sum;
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}
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// Look for an MP structure in the len bytes at addr.
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static struct mp*
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mpsearch1(uint64 a, int len)
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{
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uchar *e, *p, *addr;
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addr = P2V(a);
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e = addr+len;
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for(p = addr; p < e; p += sizeof(struct mp))
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if(memcmp(p, "_MP_", 4) == 0 && sum(p, sizeof(struct mp)) == 0)
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return (struct mp*)p;
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return 0;
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}
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// Search for the MP Floating Pointer Structure, which according to the
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// spec is in one of the following three locations:
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// 1) in the first KB of the EBDA;
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// 2) in the last KB of system base memory;
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// 3) in the BIOS ROM between 0xE0000 and 0xFFFFF.
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static struct mp*
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mpsearch(void)
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{
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uchar *bda;
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uint p;
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struct mp *mp;
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bda = (uchar *) P2V(0x400);
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if((p = ((bda[0x0F]<<8)| bda[0x0E]) << 4)){
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if((mp = mpsearch1(p, 1024)))
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return mp;
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} else {
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p = ((bda[0x14]<<8)|bda[0x13])*1024;
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if((mp = mpsearch1(p-1024, 1024)))
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return mp;
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}
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return mpsearch1(0xF0000, 0x10000);
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}
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// Search for an MP configuration table. For now,
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// don't accept the default configurations (physaddr == 0).
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// Check for correct signature, calculate the checksum and,
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// if correct, check the version.
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// To do: check extended table checksum.
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static struct mpconf*
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mpconfig(struct mp **pmp)
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{
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struct mpconf *conf;
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struct mp *mp;
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if((mp = mpsearch()) == 0 || mp->physaddr == 0)
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return 0;
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conf = (struct mpconf*) P2V((uint64) mp->physaddr);
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if(memcmp(conf, "PCMP", 4) != 0)
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return 0;
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if(conf->version != 1 && conf->version != 4)
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return 0;
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if(sum((uchar*)conf, conf->length) != 0)
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return 0;
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*pmp = mp;
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return conf;
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}
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void
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mpinit(void)
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{
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uchar *p, *e;
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int ismp;
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struct mp *mp;
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struct mpconf *conf;
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struct mpproc *proc;
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struct mpioapic *ioapic;
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if((conf = mpconfig(&mp)) == 0)
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panic("Expect to run on an SMP");
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ismp = 1;
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lapic = P2V((uint64)conf->lapicaddr_p);
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for(p=(uchar*)(conf+1), e=(uchar*)conf+conf->length; p<e; ){
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switch(*p){
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case MPPROC:
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proc = (struct mpproc*)p;
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if(ncpu < NCPU) {
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cpus[ncpu].apicid = proc->apicid; // apicid may differ from ncpu
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ncpu++;
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}
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p += sizeof(struct mpproc);
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continue;
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case MPIOAPIC:
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ioapic = (struct mpioapic*)p;
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ioapicid = ioapic->apicno;
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p += sizeof(struct mpioapic);
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continue;
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case MPBUS:
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case MPIOINTR:
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case MPLINTR:
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p += 8;
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continue;
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default:
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ismp = 0;
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break;
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}
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}
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if(!ismp)
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panic("Didn't find a suitable machine");
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if(mp->imcrp){
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// Bochs doesn't support IMCR, so this doesn't run on Bochs.
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// But it would on real hardware.
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outb(0x22, 0x70); // Select IMCR
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outb(0x23, inb(0x23) | 1); // Mask external interrupts.
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}
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}
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