ab0db651af
The x86-64 doesn't just add two levels to page tables to support 64 bit addresses, but is a different processor. For example, calling conventions, system calls, and segmentation are different from 32-bit x86. Segmentation is basically gone, but gs/fs in combination with MSRs can be used to hold a per-core pointer. In general, x86-64 is more straightforward than 32-bit x86. The port uses code from sv6 and the xv6 "rsc-amd64" branch. A summary of the changes is as follows: - Booting: switch to grub instead of xv6's bootloader (pass -kernel to qemu), because xv6's boot loader doesn't understand 64bit ELF files. And, we don't care anymore about booting. - Makefile: use -m64 instead of -m32 flag for gcc, delete boot loader, xv6.img, bochs, and memfs. For now dont' use -O2, since usertests with -O2 is bigger than MAXFILE! - Update gdb.tmpl to be for i386 or x86-64 - Console/printf: use stdarg.h and treat 64-bit addresses different from ints (32-bit) - Update elfhdr to be 64 bit - entry.S/entryother.S: add code to switch to 64-bit mode: build a simple page table in 32-bit mode before switching to 64-bit mode, share code for entering boot processor and APs, and tweak boot gdt. The boot gdt is the gdt that the kernel proper also uses. (In 64-bit mode, the gdt/segmentation and task state mostly disappear.) - exec.c: fix passing argv (64-bit now instead of 32-bit). - initcode.c: use syscall instead of int. - kernel.ld: load kernel very high, in top terabyte. 64 bits is a lot of address space! - proc.c: initial return is through new syscall path instead of trapret. - proc.h: update struct cpu to have some scratch space since syscall saves less state than int, update struct context to reflect x86-64 calling conventions. - swtch: simplify for x86-64 calling conventions. - syscall: add fetcharg to handle x86-64 calling convetions (6 arguments are passed through registers), and fetchaddr to read a 64-bit value from user space. - sysfile: update to handle pointers from user space (e.g., sys_exec), which are 64 bits. - trap.c: no special trap vector for sys calls, because x86-64 has a different plan for system calls. - trapasm: one plan for syscalls and one plan for traps (interrupt and exceptions). On x86-64, the kernel is responsible for switching user/kernel stacks. To do, xv6 keeps some scratch space in the cpu structure, and uses MSR GS_KERN_BASE to point to the core's cpu structure (using swapgs). - types.h: add uint64, and change pde_t to uint64 - usertests: exit() when fork fails, which helped in tracking down one of the bugs in the switch from 32-bit to 64-bit - vectors: update to make them 64 bits - vm.c: use bootgdt in kernel too, program MSRs for syscalls and core-local state (for swapgs), walk 4 levels in walkpgdir, add DEVSPACETOP, use task segment to set kernel stack for interrupts (but simpler than in 32-bit mode), add an extra argument to freevm (size of user part of address space) to avoid checking all entries till KERNBASE (there are MANY TB before the top 1TB). - x86: update trapframe to have 64-bit entries, which is what the processor pushes on syscalls and traps. simplify lgdt and lidt, using struct desctr, which needs the gcc directives packed and aligned. TODO: - use int32 instead of int? - simplify curproc(). xv6 has per-cpu state again, but this time it must have it. - avoid repetition in walkpgdir - fix validateint() in usertests.c - fix bugs (e.g., observed one a case of entering kernel with invalid gs or proc
224 lines
5.4 KiB
ArmAsm
224 lines
5.4 KiB
ArmAsm
# x86-64 bootstrap, assuming load by MultiBoot-compliant loader.
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# The MutliBoot specification is at:
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# http://www.gnu.org/software/grub/manual/multiboot/multiboot.html
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# GRUB is a MultiBoot loader, as is qemu's -kernel option.
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#include "mmu.h"
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#include "memlayout.h"
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# STACK is the size of the bootstrap stack.
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#define STACK 8192
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# MultiBoot header.
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# http://www.gnu.org/software/grub/manual/multiboot/multiboot.html#Header-layout
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.align 4
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.text
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.globl multiboot_header
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multiboot_header:
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#define magic 0x1badb002
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#define flags (1<<16 | 1<<0)
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.long magic
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.long flags
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.long (- magic - flags) # checksum
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.long V2P_WO(multiboot_header) # header address
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.long V2P_WO(multiboot_header) # load address
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.long V2P_WO(edata) # load end address
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.long V2P_WO(end) # bss end address
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.long V2P_WO(start) # entry address
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# Entry point jumped to by boot loader. Running in 32-bit mode.
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# http://www.gnu.org/software/grub/manual/multiboot/multiboot.html#Machine-state
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#
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# EAX = 0x2badb002
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# EBX = address of multiboot information structure
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# CS = 32-bit read/execute code segment with identity map
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# DS, ES, FS, GS, SS = 32-bit read/write data segment with identity map
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# A20 gate = enabled
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# CR0 = PE set, PG clear
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# EFLAGS = VM clear, IF clear
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#
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.code32
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.globl start
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start:
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# Tell BIOS to do "warm reboot" when we shut down.
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movw $0x1234, 0x472
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# Set up multiboot arguments for main.
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movl %eax, %edi
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movl %ebx, %esi
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# Initialize stack.
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movl $V2P_WO(stack+STACK), %esp
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# Zero bss. QEMU's MultiBoot seems not to.
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# It's possible that the header above is not right, but it looks right.
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# %edi is holding multiboot argument, so save in another register.
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# (The stack is in the bss.)
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movl %edi, %edx
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movl $V2P_WO(edata), %edi
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movl $V2P_WO(end), %ecx
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subl $V2P_WO(edata), %ecx
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movl $0, %eax
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cld
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rep stosb
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movl %edx, %edi
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call loadgdt
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# Enter new 32-bit code segment (already in 32-bit mode).
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ljmp $KCSEG32, $V2P_WO(start32) // code32 segment selector
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start32:
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# Initialize page table.
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call initpagetables
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call init32e
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movl $V2P_WO(start64), %eax
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# Enter 64-bit mode.
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ljmp $KCSEG, $V2P_WO(tramp64) // code64 segment selector
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.code64
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start64:
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# Load VA of stack
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movabsq $(stack+STACK), %rsp
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# Clear frame pointer for stack walks
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movl $0, %ebp
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# Call into C code.
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call bpmain
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# should not return from bpmain
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jmp .
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.code32
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.global apstart
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apstart:
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call loadgdt
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ljmp $KCSEG32, $V2P_WO(apstart32) // code32 segment selector
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apstart32:
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call init32e
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movl $V2P_WO(apstart64), %eax
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ljmp $KCSEG, $V2P_WO(tramp64) // code64 segment selector
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.code64
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apstart64:
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# Remember (from bootothers), that our kernel stack pointer is
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# at the top of our temporary stack.
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popq %rax
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movq %rax, %rsp
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movq $0, %rbp
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call apmain
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1: jmp 1b
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.code64
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tramp64:
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# The linker thinks we are running at tramp64, but we're actually
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# running at PADDR(tramp64), so use an explicit calculation to
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# load and jump to the correct address. %rax should hold the
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# physical address of the jmp target.
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movq $KERNBASE, %r11
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addq %r11, %rax
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jmp *%rax
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# Initial stack
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.comm stack, STACK
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# Page tables. See section 4.5 of 253668.pdf.
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# We map the first GB of physical memory at 0 and at 1 TB (not GB) before
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# the end of virtual memory. At boot time we are using the mapping at 0
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# but during ordinary execution we use the high mapping.
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# The intent is that after bootstrap the kernel can expand this mapping
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# to cover all the available physical memory.
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# This would be easier if we could use the PS bit to create GB-sized entries
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# and skip the pdt table, but not all chips support it, and QEMU doesn't.
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.align 4096
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pml4:
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.quad V2P_WO(pdpt) + PTE_P + PTE_W // present, read/write
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.quad 0
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.space 4096 - 2*16
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.quad V2P_WO(pdpt) + PTE_P + PTE_W
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.quad 0
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.align 4096
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pdpt:
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.quad V2P_WO(pdt) + PTE_P + PTE_W
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.space 4096 - 8
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.align 4096
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pdt:
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// Filled in below.
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.space 4096
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.code32
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initpagetables:
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pushl %edi
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pushl %ecx
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pushl %eax
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// Set up 64-bit entry in %edx:%eax.
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// Base address 0, present, read/write, large page.
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movl $(0 | PTE_P | PTE_W | PTE_PS), %eax
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movl $0, %edx
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// Fill in 512 entries at pdt.
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movl $V2P_WO(pdt), %edi
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movl $512, %ecx
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1:
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// Write this 64-bit entry.
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movl %eax, 0(%edi)
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movl %edx, 4(%edi)
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addl $8, %edi
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// 64-bit add to prepare address for next entry.
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// Because this is a large page entry, it covers 512 4k pages (2 MB).
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add $(512*4096), %eax
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adc $0, %edx
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loop 1b
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popl %eax
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popl %ecx
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popl %edi
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ret
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# Initialize IA-32e mode. See section 9.8.5 of 253668.pdf.
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init32e:
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# Set CR4.PAE and CR4.PSE = 1.
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movl %cr4, %eax
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orl $0x30, %eax
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movl %eax, %cr4
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# Load CR3 with physical base address of level 4 page table.
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movl $V2P_WO(pml4), %eax
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movl %eax, %cr3
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# Enable IA-32e mode by setting IA32_EFER.LME = 1.
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# Also turn on IA32_EFER.SCE (syscall enable).
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movl $0xc0000080, %ecx
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rdmsr
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orl $0x101, %eax
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wrmsr
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# Enable paging by setting CR0.PG = 1.
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movl %cr0, %eax
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orl $0x80000000, %eax
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movl %eax, %cr0
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nop
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nop
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ret
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loadgdt:
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subl $8, %esp
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movl $V2P_WO(bootgdt), 4(%esp)
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movw $(8*NSEGS-1), 2(%esp)
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lgdt 2(%esp)
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addl $8, %esp
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movl $KDSEG, %eax // data segment selector
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movw %ax, %ds
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movw %ax, %es
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movw %ax, %ss
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movl $0, %eax // null segment selector
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movw %ax, %fs
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movw %ax, %gs
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ret
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