125 lines
4.1 KiB
C
125 lines
4.1 KiB
C
/*
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* MultiProcessor Specification Version 1.[14].
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*
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* Credit: Plan 9 sources
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*/
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struct MP { /* floating pointer */
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uint8_t signature[4]; /* "_MP_" */
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physaddr_t physaddr; /* physical address of MP configuration table */
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uint8_t length; /* 1 */
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uint8_t specrev; /* [14] */
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uint8_t checksum; /* all bytes must add up to 0 */
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uint8_t type; /* MP system configuration type */
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uint8_t imcrp;
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uint8_t reserved[3];
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};
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struct MPCTB { /* configuration table header */
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uint8_t signature[4]; /* "PCMP" */
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uint16_t length; /* total table length */
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uint8_t version; /* [14] */
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uint8_t checksum; /* all bytes must add up to 0 */
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uint8_t product[20]; /* product id */
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uintptr_t oemtable; /* OEM table pointer */
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uint16_t oemlength; /* OEM table length */
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uint16_t entry; /* entry count */
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uintptr_t lapicaddr; /* address of local APIC */
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uint16_t xlength; /* extended table length */
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uint8_t xchecksum; /* extended table checksum */
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uint8_t reserved;
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};
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struct MPPE { /* processor table entry */
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uint8_t type; /* entry type (0) */
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uint8_t apicid; /* local APIC id */
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uint8_t version; /* local APIC verison */
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uint8_t flags; /* CPU flags */
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uint8_t signature[4]; /* CPU signature */
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uint32_t feature; /* feature flags from CPUID instruction */
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uint8_t reserved[8];
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};
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struct MPBE { /* bus table entry */
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uint8_t type; /* entry type (1) */
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uint8_t busno; /* bus id */
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char string[6]; /* bus type string */
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};
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struct MPIOAPIC { /* I/O APIC table entry */
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uint8_t type; /* entry type (2) */
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uint8_t apicno; /* I/O APIC id */
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uint8_t version; /* I/O APIC version */
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uint8_t flags; /* I/O APIC flags */
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uintptr_t addr; /* I/O APIC address */
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};
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struct MPIE { /* interrupt table entry */
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uint8_t type; /* entry type ([34]) */
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uint8_t intr; /* interrupt type */
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uint16_t flags; /* interrupt flag */
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uint8_t busno; /* source bus id */
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uint8_t irq; /* source bus irq */
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uint8_t apicno; /* destination APIC id */
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uint8_t intin; /* destination APIC [L]INTIN# */
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};
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enum { /* table entry types */
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MPPROCESSOR = 0x00, /* one entry per processor */
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MPBUS = 0x01, /* one entry per bus */
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MPIOAPIC = 0x02, /* one entry per I/O APIC */
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MPIOINTR = 0x03, /* one entry per bus interrupt source */
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MPLINTR = 0x04, /* one entry per system interrupt source */
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MPSASM = 0x80,
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MPHIERARCHY = 0x81,
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MPCBASM = 0x82,
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/* PCMPprocessor and PCMPioapic flags */
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MPEN = 0x01, /* enabled */
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MPBP = 0x02, /* bootstrap processor */
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/* PCMPiointr and PCMPlintr flags */
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MPPOMASK = 0x03, /* polarity conforms to specifications of bus */
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MPHIGH = 0x01, /* active high */
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MPLOW = 0x03, /* active low */
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MPELMASK = 0x0C, /* trigger mode of APIC input signals */
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MPEDGE = 0x04, /* edge-triggered */
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MPLEVEL = 0x0C, /* level-triggered */
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/* PCMPiointr and PCMPlintr interrupt type */
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MPINT = 0x00, /* vectored interrupt from APIC Rdt */
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MPNMI = 0x01, /* non-maskable interrupt */
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MPSMI = 0x02, /* system management interrupt */
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MPExtINT = 0x03, /* vectored interrupt from external PIC */
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};
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/*
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* Common bits for
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* I/O APIC Redirection Table Entry;
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* Local APIC Local Interrupt Vector Table;
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* Local APIC Inter-Processor Interrupt;
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* Local APIC Timer Vector Table.
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*/
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enum {
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APIC_FIXED = 0x00000000, /* [10:8] Delivery Mode */
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APIC_LOWEST = 0x00000100, /* Lowest priority */
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APIC_SMI = 0x00000200, /* System Management Interrupt */
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APIC_RR = 0x00000300, /* Remote Read */
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APIC_NMI = 0x00000400,
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APIC_INIT = 0x00000500, /* INIT/RESET */
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APIC_STARTUP = 0x00000600, /* Startup IPI */
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APIC_ExtINT = 0x00000700,
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APIC_PHYSICAL = 0x00000000, /* [11] Destination Mode (RW) */
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APIC_LOGICAL = 0x00000800,
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APIC_DELIVS = 0x00001000, /* [12] Delivery Status (RO) */
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APIC_HIGH = 0x00000000, /* [13] Interrupt Input Pin Polarity (RW) */
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APIC_LOW = 0x00002000,
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APIC_RemoteIRR = 0x00004000, /* [14] Remote IRR (RO) */
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APIC_EDGE = 0x00000000, /* [15] Trigger Mode (RW) */
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APIC_LEVEL = 0x00008000,
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APIC_IMASK = 0x00010000, /* [16] Interrupt Mask */
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};
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