69 lines
1.9 KiB
C
69 lines
1.9 KiB
C
#include "types.h"
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#include "param.h"
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#include "memlayout.h"
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#include "riscv.h"
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#include "defs.h"
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void main();
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// entry.S needs one stack per CPU.
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__attribute__ ((aligned (16))) char stack0[4096 * NCPU];
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// scratch area for timer interrupt, one per CPU.
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uint64 mscratch0[NCPU * 32];
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// assembly code in kernelvec.S for machine-mode timer interrupt.
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extern void timervec();
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// entry.S jumps here in machine mode on stack0.
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void
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start()
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{
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// set M Previous Privilege mode to Supervisor, for mret.
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unsigned long x = r_mstatus();
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x &= ~MSTATUS_MPP_MASK;
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x |= MSTATUS_MPP_S;
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w_mstatus(x);
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// set M Exception Program Counter to main, for mret.
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// requires gcc -mcmodel=medany
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w_mepc((uint64)main);
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// disable paging for now.
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w_satp(0);
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// delegate all interrupts and exceptions to supervisor mode.
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w_medeleg(0xffff);
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w_mideleg(0xffff);
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int id = r_mhartid();
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// set up to receive timer interrupts in machine mode,
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// which arrive at timervec in kernelvec.S,
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// which turns them into software interrupts for
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// devintr() in trap.c.
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// ask the CLINT for a timer interrupt.
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int interval = 1000000; // cycles; about 1/10th second in qemu.
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*(uint64*)CLINT_MTIMECMP(id) = *(uint64*)CLINT_MTIME + interval;
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// prepare information in scratch[] for timervec.
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// scratch[0..3] : space for timervec to save registers.
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// scratch[4] : address of CLINT MTIMECMP register.
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// scratch[5] : desired interval (in cycles) between timer interrupts.
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uint64 *scratch = &mscratch0[32 * id];
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scratch[4] = CLINT_MTIMECMP(id);
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scratch[5] = interval;
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w_mscratch((uint64)scratch);
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// set the machine-mode trap handler.
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w_mtvec((uint64)timervec);
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// enable machine-mode interrupts.
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w_mstatus(r_mstatus() | MSTATUS_MIE);
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// enable machine-mode timer interrupts.
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w_mie(r_mie() | MIE_MTIE);
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// keep each CPU's hartid in its tp register, for cpuid().
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w_tp(id);
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// switch to supervisor mode and jump to main().
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asm volatile("mret");
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}
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