125 lines
2.9 KiB
ArmAsm
125 lines
2.9 KiB
ArmAsm
#
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# interrupts and exceptions while in supervisor
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# mode come here.
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#
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# the current stack is a kernel stack.
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# push all registers, call kerneltrap().
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# when kerneltrap() returns, restore registers, return.
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#
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.globl kerneltrap
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.globl kernelvec
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.align 4
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kernelvec:
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# make room to save registers.
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addi sp, sp, -256
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# save the registers.
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sd ra, 0(sp)
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sd sp, 8(sp)
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sd gp, 16(sp)
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sd tp, 24(sp)
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sd t0, 32(sp)
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sd t1, 40(sp)
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sd t2, 48(sp)
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sd s0, 56(sp)
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sd s1, 64(sp)
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sd a0, 72(sp)
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sd a1, 80(sp)
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sd a2, 88(sp)
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sd a3, 96(sp)
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sd a4, 104(sp)
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sd a5, 112(sp)
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sd a6, 120(sp)
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sd a7, 128(sp)
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sd s2, 136(sp)
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sd s3, 144(sp)
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sd s4, 152(sp)
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sd s5, 160(sp)
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sd s6, 168(sp)
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sd s7, 176(sp)
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sd s8, 184(sp)
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sd s9, 192(sp)
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sd s10, 200(sp)
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sd s11, 208(sp)
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sd t3, 216(sp)
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sd t4, 224(sp)
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sd t5, 232(sp)
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sd t6, 240(sp)
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# call the C trap handler in trap.c
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call kerneltrap
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# restore registers.
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ld ra, 0(sp)
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ld sp, 8(sp)
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ld gp, 16(sp)
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# not tp (contains hartid), in case we moved CPUs
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ld t0, 32(sp)
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ld t1, 40(sp)
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ld t2, 48(sp)
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ld s0, 56(sp)
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ld s1, 64(sp)
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ld a0, 72(sp)
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ld a1, 80(sp)
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ld a2, 88(sp)
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ld a3, 96(sp)
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ld a4, 104(sp)
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ld a5, 112(sp)
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ld a6, 120(sp)
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ld a7, 128(sp)
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ld s2, 136(sp)
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ld s3, 144(sp)
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ld s4, 152(sp)
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ld s5, 160(sp)
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ld s6, 168(sp)
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ld s7, 176(sp)
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ld s8, 184(sp)
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ld s9, 192(sp)
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ld s10, 200(sp)
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ld s11, 208(sp)
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ld t3, 216(sp)
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ld t4, 224(sp)
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ld t5, 232(sp)
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ld t6, 240(sp)
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addi sp, sp, 256
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# return to whatever we were doing in the kernel.
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sret
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#
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# machine-mode timer interrupt.
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#
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.globl timervec
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.align 4
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timervec:
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# start.c has set up the memory that mscratch points to:
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# scratch[0,8,16] : register save area.
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# scratch[24] : address of CLINT's MTIMECMP register.
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# scratch[32] : desired interval between interrupts.
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csrrw a0, mscratch, a0
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sd a1, 0(a0)
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sd a2, 8(a0)
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sd a3, 16(a0)
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# schedule the next timer interrupt
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# by adding interval to mtimecmp.
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ld a1, 24(a0) # CLINT_MTIMECMP(hart)
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ld a2, 32(a0) # interval
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ld a3, 0(a1)
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add a3, a3, a2
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sd a3, 0(a1)
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# arrange for a supervisor software interrupt
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# after this handler returns.
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li a1, 2
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csrw sip, a1
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ld a3, 16(a0)
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ld a2, 8(a0)
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ld a1, 0(a0)
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csrrw a0, mscratch, a0
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mret
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