ab0db651af
The x86-64 doesn't just add two levels to page tables to support 64 bit addresses, but is a different processor. For example, calling conventions, system calls, and segmentation are different from 32-bit x86. Segmentation is basically gone, but gs/fs in combination with MSRs can be used to hold a per-core pointer. In general, x86-64 is more straightforward than 32-bit x86. The port uses code from sv6 and the xv6 "rsc-amd64" branch. A summary of the changes is as follows: - Booting: switch to grub instead of xv6's bootloader (pass -kernel to qemu), because xv6's boot loader doesn't understand 64bit ELF files. And, we don't care anymore about booting. - Makefile: use -m64 instead of -m32 flag for gcc, delete boot loader, xv6.img, bochs, and memfs. For now dont' use -O2, since usertests with -O2 is bigger than MAXFILE! - Update gdb.tmpl to be for i386 or x86-64 - Console/printf: use stdarg.h and treat 64-bit addresses different from ints (32-bit) - Update elfhdr to be 64 bit - entry.S/entryother.S: add code to switch to 64-bit mode: build a simple page table in 32-bit mode before switching to 64-bit mode, share code for entering boot processor and APs, and tweak boot gdt. The boot gdt is the gdt that the kernel proper also uses. (In 64-bit mode, the gdt/segmentation and task state mostly disappear.) - exec.c: fix passing argv (64-bit now instead of 32-bit). - initcode.c: use syscall instead of int. - kernel.ld: load kernel very high, in top terabyte. 64 bits is a lot of address space! - proc.c: initial return is through new syscall path instead of trapret. - proc.h: update struct cpu to have some scratch space since syscall saves less state than int, update struct context to reflect x86-64 calling conventions. - swtch: simplify for x86-64 calling conventions. - syscall: add fetcharg to handle x86-64 calling convetions (6 arguments are passed through registers), and fetchaddr to read a 64-bit value from user space. - sysfile: update to handle pointers from user space (e.g., sys_exec), which are 64 bits. - trap.c: no special trap vector for sys calls, because x86-64 has a different plan for system calls. - trapasm: one plan for syscalls and one plan for traps (interrupt and exceptions). On x86-64, the kernel is responsible for switching user/kernel stacks. To do, xv6 keeps some scratch space in the cpu structure, and uses MSR GS_KERN_BASE to point to the core's cpu structure (using swapgs). - types.h: add uint64, and change pde_t to uint64 - usertests: exit() when fork fails, which helped in tracking down one of the bugs in the switch from 32-bit to 64-bit - vectors: update to make them 64 bits - vm.c: use bootgdt in kernel too, program MSRs for syscalls and core-local state (for swapgs), walk 4 levels in walkpgdir, add DEVSPACETOP, use task segment to set kernel stack for interrupts (but simpler than in 32-bit mode), add an extra argument to freevm (size of user part of address space) to avoid checking all entries till KERNBASE (there are MANY TB before the top 1TB). - x86: update trapframe to have 64-bit entries, which is what the processor pushes on syscalls and traps. simplify lgdt and lidt, using struct desctr, which needs the gcc directives packed and aligned. TODO: - use int32 instead of int? - simplify curproc(). xv6 has per-cpu state again, but this time it must have it. - avoid repetition in walkpgdir - fix validateint() in usertests.c - fix bugs (e.g., observed one a case of entering kernel with invalid gs or proc
172 lines
3 KiB
C
172 lines
3 KiB
C
// Routines to let C code use special x86 instructions.
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#ifndef __ASSEMBLER__
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static inline uchar
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inb(ushort port)
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{
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uchar data;
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asm volatile("in %1,%0" : "=a" (data) : "d" (port));
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return data;
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}
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static inline void
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insl(int port, void *addr, int cnt)
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{
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asm volatile("cld; rep insl" :
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"=D" (addr), "=c" (cnt) :
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"d" (port), "0" (addr), "1" (cnt) :
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"memory", "cc");
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}
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static inline void
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outb(ushort port, uchar data)
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{
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asm volatile("out %0,%1" : : "a" (data), "d" (port));
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}
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static inline void
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outw(ushort port, ushort data)
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{
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asm volatile("out %0,%1" : : "a" (data), "d" (port));
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}
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static inline void
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outsl(int port, const void *addr, int cnt)
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{
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asm volatile("cld; rep outsl" :
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"=S" (addr), "=c" (cnt) :
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"d" (port), "0" (addr), "1" (cnt) :
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"cc");
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}
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static inline void
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stosb(void *addr, int data, int cnt)
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{
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asm volatile("cld; rep stosb" :
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"=D" (addr), "=c" (cnt) :
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"0" (addr), "1" (cnt), "a" (data) :
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"memory", "cc");
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}
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static inline void
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stosl(void *addr, int data, int cnt)
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{
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asm volatile("cld; rep stosl" :
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"=D" (addr), "=c" (cnt) :
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"0" (addr), "1" (cnt), "a" (data) :
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"memory", "cc");
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}
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static inline void
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lgdt(void *p)
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{
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asm volatile("lgdt (%0)" : : "r" (p) : "memory");
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}
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static inline void
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lidt(void *p)
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{
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asm volatile("lidt (%0)" : : "r" (p) : "memory");
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}
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static inline void
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ltr(ushort sel)
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{
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asm volatile("ltr %0" : : "r" (sel));
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}
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static inline uint64
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readeflags(void)
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{
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uint64 eflags;
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asm volatile("pushf; pop %0" : "=r" (eflags));
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return eflags;
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}
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static inline void
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loadgs(ushort v)
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{
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asm volatile("movw %0, %%gs" : : "r" (v));
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}
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static inline void
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cli(void)
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{
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asm volatile("cli");
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}
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static inline void
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sti(void)
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{
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asm volatile("sti");
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}
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static inline uint
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xchg(volatile uint *addr, uint newval)
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{
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uint result;
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// The + in "+m" denotes a read-modify-write operand.
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asm volatile("lock; xchgl %0, %1" :
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"+m" (*addr), "=a" (result) :
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"1" (newval) :
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"cc");
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return result;
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}
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static inline uint
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rcr2(void)
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{
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uint64 val;
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asm volatile("mov %%cr2,%0" : "=r" (val));
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return val;
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}
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static inline void
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lcr3(uint64 val)
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{
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asm volatile("mov %0,%%cr3" : : "r" (val));
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}
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static inline void
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writegs(uint16 v)
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{
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__asm volatile("movw %0, %%gs" : : "r" (v));
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}
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//PAGEBREAK: 36
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// Layout of the trap frame built on the stack by the
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// hardware and by trapasm.S, and passed to trap().
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struct trapframe {
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uint64 rax;
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uint64 rbx;
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uint64 rcx;
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uint64 rdx;
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uint64 rbp;
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uint64 rsi;
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uint64 rdi;
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uint64 r8;
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uint64 r9;
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uint64 r10;
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uint64 r11;
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uint64 r12;
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uint64 r13;
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uint64 r14;
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uint64 r15;
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uint64 trapno;
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uint64 err;
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uint64 rip;
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uint16 cs;
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uint16 padding[3];
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uint64 rflags;
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uint64 rsp;
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uint64 ss;
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}__attribute__((packed));
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#endif
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#define TF_CS 144 // offset in trapframe for saved cs
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