2007-11-02 18:56:58 +00:00
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/*
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* $Source$
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* $State$
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*/
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/* Integer registers */
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0, GPR, 0, "r0",
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0, GPR, 1, "r1",
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0, GPR, 1, "sp",
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0, GPR, 2, "r2",
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0, GPR, 2, "fp",
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0, GPR, 3, "r3",
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0, GPR, 4, "r4",
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0, GPR, 5, "r5",
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0, GPR, 6, "r6",
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0, GPR, 7, "r7",
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0, GPR, 8, "r8",
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0, GPR, 9, "r9",
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0, GPR, 10, "r10",
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0, GPR, 11, "r11",
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0, GPR, 12, "r12",
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0, GPR, 13, "r13",
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0, GPR, 14, "r14",
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0, GPR, 15, "r15",
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0, GPR, 16, "r16",
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0, GPR, 17, "r17",
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0, GPR, 18, "r18",
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0, GPR, 19, "r19",
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0, GPR, 20, "r20",
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0, GPR, 21, "r21",
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0, GPR, 22, "r22",
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0, GPR, 23, "r23",
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0, GPR, 24, "r24",
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0, GPR, 25, "r25",
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0, GPR, 26, "r26",
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0, GPR, 27, "r27",
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0, GPR, 28, "r28",
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0, GPR, 29, "r29",
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0, GPR, 30, "r30",
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0, GPR, 31, "r31",
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/* Floating-point registers */
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0, FPR, 0, "f0",
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0, FPR, 1, "f1",
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0, FPR, 2, "f2",
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0, FPR, 3, "f3",
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0, FPR, 4, "f4",
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0, FPR, 5, "f5",
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0, FPR, 6, "f6",
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0, FPR, 7, "f7",
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0, FPR, 8, "f8",
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0, FPR, 9, "f9",
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0, FPR, 10, "f10",
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0, FPR, 11, "f11",
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0, FPR, 12, "f12",
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0, FPR, 13, "f13",
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0, FPR, 14, "f14",
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0, FPR, 15, "f15",
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0, FPR, 16, "f16",
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0, FPR, 17, "f17",
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0, FPR, 18, "f18",
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0, FPR, 19, "f19",
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0, FPR, 20, "f20",
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0, FPR, 21, "f21",
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0, FPR, 22, "f22",
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0, FPR, 23, "f23",
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0, FPR, 24, "f24",
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0, FPR, 25, "f25",
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0, FPR, 26, "f26",
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0, FPR, 27, "f27",
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0, FPR, 28, "f28",
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0, FPR, 29, "f29",
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0, FPR, 30, "f30",
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0, FPR, 31, "f31",
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/* Special registers */
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0, SPR, 32, "xer",
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0, SPR, 256, "lr",
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0, SPR, 288, "ctr",
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/* Condition registers */
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0, CR, 0, "cr0",
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0, CR, 1, "cr1",
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0, CR, 2, "cr2",
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0, CR, 3, "cr3",
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0, CR, 4, "cr4",
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0, CR, 5, "cr5",
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0, CR, 6, "cr6",
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0, CR, 7, "cr7",
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/* Condition code flag */
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0, C, 0, ".",
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/* Special instructions */
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2016-09-18 21:03:23 +00:00
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0, OP_LI32, 0, "li32",
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2017-01-15 10:59:33 +00:00
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0, OP_HI, 0, "hi16",
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0, OP_HA, 0, "ha16",
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2017-01-15 09:21:02 +00:00
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0, OP_LO, 0, "lo16",
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2007-11-02 18:56:58 +00:00
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/* Branch processor instructions (page 20) */
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0, OP_LIL, 18<<26 | 0<<1 | 0<<0, "b",
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0, OP_LIA, 18<<26 | 1<<1 | 0<<0, "ba",
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0, OP_LIL, 18<<26 | 0<<1 | 1<<0, "bl",
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0, OP_LIA, 18<<26 | 1<<1 | 1<<0, "bla",
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0, OP_BO_BI_BDL, 16<<26 | 0<<1 | 0<<0, "bc",
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0, OP_BO_BI_BDA, 16<<26 | 1<<1 | 0<<0, "bca",
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0, OP_BO_BI_BDL, 16<<26 | 0<<1 | 1<<0, "bcl",
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0, OP_BO_BI_BDA, 16<<26 | 1<<1 | 1<<0, "bcla",
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0, OP_BO_BI_BH, 19<<26 | 16<<1 | 0<<0, "bclr",
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0, OP_BO_BI_BH, 19<<26 | 16<<1 | 1<<0, "bclrl",
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0, OP_BO_BI_BH, 19<<26 | 528<<1 | 0<<0, "bcctr",
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0, OP_BO_BI_BH, 19<<26 | 528<<1 | 1<<0, "bcctrl",
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0, OP_LEV, 17<<26 | 1<<1, "sc",
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0, OP_BT_BA_BB, 19<<26 | 257<<1, "crand",
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0, OP_BT_BA_BB, 19<<26 | 449<<1, "cror",
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0, OP_BT_BA_BB, 19<<26 | 193<<1, "crxor",
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0, OP_BT_BA_BB, 19<<26 | 225<<1, "crnand",
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0, OP_BT_BA_BB, 19<<26 | 33<<1, "crnor",
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Teach the assembler about PowerPC extended mnemonics.
Also make a few changes to basic mnemonics. Fix typo in name of the
basic "creqv". Add the basic "addc" and relatives, because it would
be odd to have the extended "subc" without "addc". Fix the basic
"rldicl", "rldicr", "rldic", "rldimi" to correctly encode the 6-bit MB
field. Fix "slw" and relatives to correctly swap their RA and RS
operands.
Add many, but not all, of the extended mnemonics from IBM's Power ISA
Version 2.06 Book I Appendix E. (I used 2.06, published 2009, just
because I already had the PDF of it.) This commit includes mnemonics
for branching, subtraction, traps, bit rotation, and a few others,
like "mflr" and "nop". The assembler now understands branches like
`beq cr7, label` and bit shifts like `slwi r7, r7, 2`. These encode
the same machine instructions as the basic "bc" and "rlwinm".
Some operands to basic names become optional. The assembler no longer
requires the level in "sc" or the branch hint in "bcctr" and "bclr";
they default to zero. Some extended names take an optional branch
hint or condition register.
Some extended names are still missing. I don't provide names with
static branch prediction, like "beq+" or "bge-", because the assembler
parses '+' and '-' as operators, not as part of an instruction name.
I also don't provide some names that 2.06 has for moving to or from
the condition register or some special purpose registers, names like
"mtcr" or "mfuamr".
This commit also deletes some unused tokens and one unused yacc rule.
2017-01-22 04:49:29 +00:00
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0, OP_BT_BA_BB, 19<<26 | 289<<1, "creqv",
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2007-11-02 18:56:58 +00:00
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0, OP_BT_BA_BB, 19<<26 | 129<<1, "crandc",
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0, OP_BT_BA_BB, 19<<26 | 417<<1, "crorc",
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0, OP_BF_BFA, 19<<26 | 0<<1, "mcrf",
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Teach the assembler about PowerPC extended mnemonics.
Also make a few changes to basic mnemonics. Fix typo in name of the
basic "creqv". Add the basic "addc" and relatives, because it would
be odd to have the extended "subc" without "addc". Fix the basic
"rldicl", "rldicr", "rldic", "rldimi" to correctly encode the 6-bit MB
field. Fix "slw" and relatives to correctly swap their RA and RS
operands.
Add many, but not all, of the extended mnemonics from IBM's Power ISA
Version 2.06 Book I Appendix E. (I used 2.06, published 2009, just
because I already had the PDF of it.) This commit includes mnemonics
for branching, subtraction, traps, bit rotation, and a few others,
like "mflr" and "nop". The assembler now understands branches like
`beq cr7, label` and bit shifts like `slwi r7, r7, 2`. These encode
the same machine instructions as the basic "bc" and "rlwinm".
Some operands to basic names become optional. The assembler no longer
requires the level in "sc" or the branch hint in "bcctr" and "bclr";
they default to zero. Some extended names take an optional branch
hint or condition register.
Some extended names are still missing. I don't provide names with
static branch prediction, like "beq+" or "bge-", because the assembler
parses '+' and '-' as operators, not as part of an instruction name.
I also don't provide some names that 2.06 has for moving to or from
the condition register or some special purpose registers, names like
"mtcr" or "mfuamr".
This commit also deletes some unused tokens and one unused yacc rule.
2017-01-22 04:49:29 +00:00
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/* extended mnemonics for bc, bcctr, bclr */
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0, OP_BH, 19<<26 | 20<<21 | 528<<1 | 0<<0, "bctr",
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0, OP_BH, 19<<26 | 20<<21 | 528<<1 | 1<<0, "bctrl",
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0, OP_BDL, 16<<26 | 16<<21 | 0<<1 | 0<<0, "bdnz",
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0, OP_BDA, 16<<26 | 16<<21 | 1<<1 | 0<<0, "bdnza",
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0, OP_BH, 19<<26 | 16<<21 | 16<<1 | 0<<0, "bdnzlr",
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0, OP_BDL, 16<<26 | 16<<21 | 0<<1 | 1<<0, "bdnzl",
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0, OP_BDA, 16<<26 | 16<<21 | 1<<1 | 1<<0, "bdnzla",
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0, OP_BH, 19<<26 | 16<<21 | 16<<1 | 1<<0, "bdnzlrl",
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0, OP_BI_BDL, 16<<26 | 0<<21 | 0<<1 | 0<<0, "bdnzf",
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0, OP_BI_BDA, 16<<26 | 0<<21 | 1<<1 | 0<<0, "bdnzfa",
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0, OP_BI_BH, 19<<26 | 0<<21 | 16<<1 | 0<<0, "bdnzflr",
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0, OP_BI_BDL, 16<<26 | 0<<21 | 0<<1 | 1<<0, "bdnzfl",
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0, OP_BI_BDA, 16<<26 | 0<<21 | 1<<1 | 1<<0, "bdnzfla",
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0, OP_BI_BH, 19<<26 | 0<<21 | 16<<1 | 1<<0, "bdnzflrl",
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0, OP_BI_BDL, 16<<26 | 8<<21 | 0<<1 | 0<<0, "bdnzt",
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0, OP_BI_BDA, 16<<26 | 8<<21 | 1<<1 | 0<<0, "bdnzta",
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0, OP_BI_BH, 19<<26 | 8<<21 | 16<<1 | 0<<0, "bdnztlr",
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0, OP_BI_BDL, 16<<26 | 8<<21 | 0<<1 | 1<<0, "bdnztl",
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0, OP_BI_BDA, 16<<26 | 8<<21 | 1<<1 | 1<<0, "bdnztla",
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0, OP_BI_BH, 19<<26 | 8<<21 | 16<<1 | 1<<0, "bdnztlrl",
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0, OP_BDL, 16<<26 | 18<<21 | 0<<1 | 0<<0, "bdz",
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0, OP_BDA, 16<<26 | 18<<21 | 1<<1 | 0<<0, "bdza",
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0, OP_BH, 19<<26 | 18<<21 | 16<<1 | 0<<0, "bdzlr",
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0, OP_BDL, 16<<26 | 18<<21 | 0<<1 | 1<<0, "bdzl",
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0, OP_BDA, 16<<26 | 18<<21 | 1<<1 | 1<<0, "bdzla",
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0, OP_BH, 19<<26 | 18<<21 | 16<<1 | 1<<0, "bdzlrl",
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0, OP_BI_BDL, 16<<26 | 2<<21 | 0<<1 | 0<<0, "bdzf",
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0, OP_BI_BDA, 16<<26 | 2<<21 | 1<<1 | 0<<0, "bdzfa",
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0, OP_BI_BH, 19<<26 | 2<<21 | 16<<1 | 0<<0, "bdzflr",
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0, OP_BI_BDL, 16<<26 | 2<<21 | 0<<1 | 1<<0, "bdzfl",
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0, OP_BI_BDA, 16<<26 | 2<<21 | 1<<1 | 1<<0, "bdzfla",
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0, OP_BI_BH, 19<<26 | 2<<21 | 16<<1 | 1<<0, "bdzflrl",
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0, OP_BI_BDL, 16<<26 | 10<<21 | 0<<1 | 0<<0, "bdzt",
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0, OP_BI_BDA, 16<<26 | 10<<21 | 1<<1 | 0<<0, "bdzta",
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0, OP_BI_BH, 19<<26 | 10<<21 | 16<<1 | 0<<0, "bdztlr",
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0, OP_BI_BDL, 16<<26 | 10<<21 | 0<<1 | 1<<0, "bdztl",
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0, OP_BI_BDA, 16<<26 | 10<<21 | 1<<1 | 1<<0, "bdztla",
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0, OP_BI_BH, 19<<26 | 10<<21 | 16<<1 | 1<<0, "bdztlrl",
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0, OP_BI_BDL, 16<<26 | 4<<21 | 0<<1 | 0<<0, "bf",
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0, OP_BI_BDA, 16<<26 | 4<<21 | 1<<1 | 0<<0, "bfa",
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0, OP_BI_BH, 19<<26 | 4<<21 | 528<<1 | 0<<0, "bfctr",
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0, OP_BI_BH, 19<<26 | 4<<21 | 528<<1 | 1<<0, "bfctrl",
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0, OP_BI_BDL, 16<<26 | 4<<21 | 0<<1 | 1<<0, "bfl",
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0, OP_BI_BDA, 16<<26 | 4<<21 | 0<<1 | 1<<0, "bfla",
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0, OP_BI_BH, 19<<26 | 4<<21 | 16<<1 | 0<<0, "bflr",
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0, OP_BI_BH, 19<<26 | 4<<21 | 16<<1 | 1<<0, "bflrl",
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0, OP_BH, 19<<26 | 20<<21 | 16<<1 | 0<<0, "blr",
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0, OP_BH, 19<<26 | 20<<21 | 16<<1 | 1<<0, "blrl",
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0, OP_BI_BDL, 16<<26 | 12<<21 | 0<<1 | 0<<0, "bt",
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0, OP_BI_BDA, 16<<26 | 12<<21 | 1<<1 | 0<<0, "bta",
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0, OP_BI_BH, 19<<26 | 12<<21 | 528<<1 | 0<<0, "btctr",
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0, OP_BI_BH, 19<<26 | 12<<21 | 528<<1 | 1<<0, "btctrl",
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0, OP_BI_BDL, 16<<26 | 12<<21 | 0<<1 | 1<<0, "btl",
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0, OP_BI_BDA, 16<<26 | 12<<21 | 0<<1 | 1<<0, "btla",
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0, OP_BI_BH, 19<<26 | 12<<21 | 16<<1 | 0<<0, "btlr",
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0, OP_BI_BH, 19<<26 | 12<<21 | 16<<1 | 1<<0, "btlrl",
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/* extended m with condition in BI */
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0, OP_BICR_BDL, 16<<26 | 12<<21 | 2<<16 | 0<<1 | 0<<0, "beq",
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0, OP_BICR_BDA, 16<<26 | 12<<21 | 2<<16 | 1<<1 | 0<<0, "beqa",
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0, OP_BICR_BH, 19<<26 | 12<<21 | 2<<16 | 528<<1 | 0<<0, "beqctr",
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0, OP_BICR_BH, 19<<26 | 12<<21 | 2<<16 | 528<<1 | 1<<0, "beqctrl",
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0, OP_BICR_BDL, 16<<26 | 12<<21 | 2<<16 | 0<<1 | 1<<0, "beql",
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0, OP_BICR_BDA, 16<<26 | 12<<21 | 2<<16 | 1<<1 | 1<<0, "beqla",
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0, OP_BICR_BH, 19<<26 | 12<<21 | 2<<16 | 16<<1 | 0<<0, "beqlr",
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0, OP_BICR_BH, 19<<26 | 12<<21 | 2<<16 | 16<<1 | 1<<0, "beqlrl",
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0, OP_BICR_BDL, 16<<26 | 4<<21 | 0<<16 | 0<<1 | 0<<0, "bge",
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0, OP_BICR_BDA, 16<<26 | 4<<21 | 0<<16 | 1<<1 | 0<<0, "bgea",
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0, OP_BICR_BH, 19<<26 | 4<<21 | 0<<16 | 528<<1 | 0<<0, "bgectr",
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0, OP_BICR_BH, 19<<26 | 4<<21 | 0<<16 | 528<<1 | 1<<0, "bgectrl",
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0, OP_BICR_BDL, 16<<26 | 4<<21 | 0<<16 | 0<<1 | 1<<0, "bgel",
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0, OP_BICR_BDA, 16<<26 | 4<<21 | 0<<16 | 1<<1 | 1<<0, "bgela",
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0, OP_BICR_BH, 19<<26 | 4<<21 | 0<<16 | 16<<1 | 0<<0, "bgelr",
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0, OP_BICR_BH, 19<<26 | 4<<21 | 0<<16 | 16<<1 | 1<<0, "bgelrl",
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0, OP_BICR_BDL, 16<<26 | 12<<21 | 1<<16 | 0<<1 | 0<<0, "bgt",
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0, OP_BICR_BDA, 16<<26 | 12<<21 | 1<<16 | 1<<1 | 0<<0, "bgta",
|
|
|
|
|
0, OP_BICR_BH, 19<<26 | 12<<21 | 1<<16 | 528<<1 | 0<<0, "bgtctr",
|
|
|
|
|
0, OP_BICR_BH, 19<<26 | 12<<21 | 1<<16 | 528<<1 | 1<<0, "bgtctrl",
|
|
|
|
|
0, OP_BICR_BDL, 16<<26 | 12<<21 | 1<<16 | 0<<1 | 1<<0, "bgtl",
|
|
|
|
|
0, OP_BICR_BDA, 16<<26 | 12<<21 | 1<<16 | 1<<1 | 1<<0, "bgtla",
|
|
|
|
|
0, OP_BICR_BH, 19<<26 | 12<<21 | 1<<16 | 16<<1 | 0<<0, "bgtlr",
|
|
|
|
|
0, OP_BICR_BH, 19<<26 | 12<<21 | 1<<16 | 16<<1 | 1<<0, "bgtlrl",
|
|
|
|
|
0, OP_BICR_BDL, 16<<26 | 4<<21 | 1<<16 | 0<<1 | 0<<0, "ble",
|
|
|
|
|
0, OP_BICR_BDA, 16<<26 | 4<<21 | 1<<16 | 1<<1 | 0<<0, "blea",
|
|
|
|
|
0, OP_BICR_BH, 19<<26 | 4<<21 | 1<<16 | 528<<1 | 0<<0, "blectr",
|
|
|
|
|
0, OP_BICR_BH, 19<<26 | 4<<21 | 1<<16 | 528<<1 | 1<<0, "blectrl",
|
|
|
|
|
0, OP_BICR_BDL, 16<<26 | 4<<21 | 1<<16 | 0<<1 | 1<<0, "blel",
|
|
|
|
|
0, OP_BICR_BDA, 16<<26 | 4<<21 | 1<<16 | 1<<1 | 1<<0, "blela",
|
|
|
|
|
0, OP_BICR_BH, 19<<26 | 4<<21 | 1<<16 | 16<<1 | 0<<0, "blelr",
|
|
|
|
|
0, OP_BICR_BH, 19<<26 | 4<<21 | 1<<16 | 16<<1 | 1<<0, "blelrl",
|
|
|
|
|
0, OP_BICR_BDL, 16<<26 | 12<<21 | 0<<16 | 0<<1 | 0<<0, "blt",
|
|
|
|
|
0, OP_BICR_BDA, 16<<26 | 12<<21 | 0<<16 | 1<<1 | 0<<0, "blta",
|
|
|
|
|
0, OP_BICR_BH, 19<<26 | 12<<21 | 0<<16 | 528<<1 | 0<<0, "bltctr",
|
|
|
|
|
0, OP_BICR_BH, 19<<26 | 12<<21 | 0<<16 | 528<<1 | 1<<0, "bltctrl",
|
|
|
|
|
0, OP_BICR_BDL, 16<<26 | 12<<21 | 0<<16 | 0<<1 | 1<<0, "bltl",
|
|
|
|
|
0, OP_BICR_BDA, 16<<26 | 12<<21 | 0<<16 | 1<<1 | 1<<0, "bltla",
|
|
|
|
|
0, OP_BICR_BH, 19<<26 | 12<<21 | 0<<16 | 16<<1 | 0<<0, "bltlr",
|
|
|
|
|
0, OP_BICR_BH, 19<<26 | 12<<21 | 0<<16 | 16<<1 | 1<<0, "bltlrl",
|
|
|
|
|
0, OP_BICR_BDL, 16<<26 | 4<<21 | 2<<16 | 0<<1 | 0<<0, "bne",
|
|
|
|
|
0, OP_BICR_BDA, 16<<26 | 4<<21 | 2<<16 | 1<<1 | 0<<0, "bnea",
|
|
|
|
|
0, OP_BICR_BH, 19<<26 | 4<<21 | 2<<16 | 528<<1 | 0<<0, "bnectr",
|
|
|
|
|
0, OP_BICR_BH, 19<<26 | 4<<21 | 2<<16 | 528<<1 | 1<<0, "bnectrl",
|
|
|
|
|
0, OP_BICR_BDL, 16<<26 | 4<<21 | 2<<16 | 0<<1 | 1<<0, "bnel",
|
|
|
|
|
0, OP_BICR_BDA, 16<<26 | 4<<21 | 2<<16 | 1<<1 | 1<<0, "bnela",
|
|
|
|
|
0, OP_BICR_BH, 19<<26 | 4<<21 | 2<<16 | 16<<1 | 0<<0, "bnelr",
|
|
|
|
|
0, OP_BICR_BH, 19<<26 | 4<<21 | 2<<16 | 16<<1 | 1<<0, "bnelrl",
|
|
|
|
|
0, OP_BICR_BDL, 16<<26 | 4<<21 | 1<<16 | 0<<1 | 0<<0, "bng",
|
|
|
|
|
0, OP_BICR_BDA, 16<<26 | 4<<21 | 1<<16 | 1<<1 | 0<<0, "bnga",
|
|
|
|
|
0, OP_BICR_BH, 19<<26 | 4<<21 | 1<<16 | 528<<1 | 0<<0, "bngctr",
|
|
|
|
|
0, OP_BICR_BH, 19<<26 | 4<<21 | 1<<16 | 528<<1 | 1<<0, "bngctrl",
|
|
|
|
|
0, OP_BICR_BDL, 16<<26 | 4<<21 | 1<<16 | 0<<1 | 1<<0, "bngl",
|
|
|
|
|
0, OP_BICR_BDA, 16<<26 | 4<<21 | 1<<16 | 1<<1 | 1<<0, "bngla",
|
|
|
|
|
0, OP_BICR_BH, 19<<26 | 4<<21 | 1<<16 | 16<<1 | 0<<0, "bnglr",
|
|
|
|
|
0, OP_BICR_BH, 19<<26 | 4<<21 | 1<<16 | 16<<1 | 1<<0, "bnglrl",
|
|
|
|
|
0, OP_BICR_BDL, 16<<26 | 4<<21 | 0<<16 | 0<<1 | 0<<0, "bnl",
|
|
|
|
|
0, OP_BICR_BDA, 16<<26 | 4<<21 | 0<<16 | 1<<1 | 0<<0, "bnla",
|
|
|
|
|
0, OP_BICR_BH, 19<<26 | 4<<21 | 0<<16 | 528<<1 | 0<<0, "bnlctr",
|
|
|
|
|
0, OP_BICR_BH, 19<<26 | 4<<21 | 0<<16 | 528<<1 | 1<<0, "bnlctrl",
|
|
|
|
|
0, OP_BICR_BDL, 16<<26 | 4<<21 | 0<<16 | 0<<1 | 1<<0, "bnll",
|
|
|
|
|
0, OP_BICR_BDA, 16<<26 | 4<<21 | 0<<16 | 1<<1 | 1<<0, "bnlla",
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|
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|
|
0, OP_BICR_BH, 19<<26 | 4<<21 | 0<<16 | 16<<1 | 0<<0, "bnllr",
|
|
|
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|
0, OP_BICR_BH, 19<<26 | 4<<21 | 0<<16 | 16<<1 | 1<<0, "bnllrl",
|
|
|
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|
0, OP_BICR_BDL, 16<<26 | 4<<21 | 3<<16 | 0<<1 | 0<<0, "bns",
|
|
|
|
|
0, OP_BICR_BDA, 16<<26 | 4<<21 | 3<<16 | 1<<1 | 0<<0, "bnsa",
|
|
|
|
|
0, OP_BICR_BH, 19<<26 | 4<<21 | 3<<16 | 528<<1 | 0<<0, "bnsctr",
|
|
|
|
|
0, OP_BICR_BH, 19<<26 | 4<<21 | 3<<16 | 528<<1 | 1<<0, "bnsctrl",
|
|
|
|
|
0, OP_BICR_BDL, 16<<26 | 4<<21 | 3<<16 | 0<<1 | 1<<0, "bnsl",
|
|
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|
|
0, OP_BICR_BDA, 16<<26 | 4<<21 | 3<<16 | 1<<1 | 1<<0, "bnsla",
|
|
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|
0, OP_BICR_BH, 19<<26 | 4<<21 | 3<<16 | 16<<1 | 0<<0, "bnslr",
|
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|
0, OP_BICR_BH, 19<<26 | 4<<21 | 3<<16 | 16<<1 | 1<<0, "bnslrl",
|
|
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|
|
0, OP_BICR_BDL, 16<<26 | 4<<21 | 3<<16 | 0<<1 | 0<<0, "bnu",
|
|
|
|
|
0, OP_BICR_BDA, 16<<26 | 4<<21 | 3<<16 | 1<<1 | 0<<0, "bnua",
|
|
|
|
|
0, OP_BICR_BH, 19<<26 | 4<<21 | 3<<16 | 528<<1 | 0<<0, "bnuctr",
|
|
|
|
|
0, OP_BICR_BH, 19<<26 | 4<<21 | 3<<16 | 528<<1 | 1<<0, "bnuctrl",
|
|
|
|
|
0, OP_BICR_BDL, 16<<26 | 4<<21 | 3<<16 | 0<<1 | 1<<0, "bnul",
|
|
|
|
|
0, OP_BICR_BDA, 16<<26 | 4<<21 | 3<<16 | 1<<1 | 1<<0, "bnula",
|
|
|
|
|
0, OP_BICR_BH, 19<<26 | 4<<21 | 3<<16 | 16<<1 | 0<<0, "bnulr",
|
|
|
|
|
0, OP_BICR_BH, 19<<26 | 4<<21 | 3<<16 | 16<<1 | 1<<0, "bnulrl",
|
|
|
|
|
0, OP_BICR_BDL, 16<<26 | 12<<21 | 3<<16 | 0<<1 | 0<<0, "bso",
|
|
|
|
|
0, OP_BICR_BDA, 16<<26 | 12<<21 | 3<<16 | 1<<1 | 0<<0, "bsoa",
|
|
|
|
|
0, OP_BICR_BH, 19<<26 | 12<<21 | 3<<16 | 528<<1 | 0<<0, "bsoctr",
|
|
|
|
|
0, OP_BICR_BH, 19<<26 | 12<<21 | 3<<16 | 528<<1 | 1<<0, "bsoctrl",
|
|
|
|
|
0, OP_BICR_BDL, 16<<26 | 12<<21 | 3<<16 | 0<<1 | 1<<0, "bsol",
|
|
|
|
|
0, OP_BICR_BDA, 16<<26 | 12<<21 | 3<<16 | 1<<1 | 1<<0, "bsola",
|
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|
0, OP_BICR_BH, 19<<26 | 12<<21 | 3<<16 | 16<<1 | 0<<0, "bsolr",
|
|
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|
|
0, OP_BICR_BH, 19<<26 | 12<<21 | 3<<16 | 16<<1 | 1<<0, "bsolrl",
|
|
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|
|
0, OP_BICR_BDL, 16<<26 | 12<<21 | 3<<16 | 0<<1 | 0<<0, "bun",
|
|
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|
|
0, OP_BICR_BDA, 16<<26 | 12<<21 | 3<<16 | 1<<1 | 0<<0, "buna",
|
|
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|
|
0, OP_BICR_BH, 19<<26 | 12<<21 | 3<<16 | 528<<1 | 0<<0, "bunctr",
|
|
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|
|
0, OP_BICR_BH, 19<<26 | 12<<21 | 3<<16 | 528<<1 | 1<<0, "bunctrl",
|
|
|
|
|
0, OP_BICR_BDL, 16<<26 | 12<<21 | 3<<16 | 0<<1 | 1<<0, "bunl",
|
|
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|
|
0, OP_BICR_BDA, 16<<26 | 12<<21 | 3<<16 | 1<<1 | 1<<0, "bunla",
|
|
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|
|
0, OP_BICR_BH, 19<<26 | 12<<21 | 3<<16 | 16<<1 | 0<<0, "bunlr",
|
|
|
|
|
0, OP_BICR_BH, 19<<26 | 12<<21 | 3<<16 | 16<<1 | 1<<0, "bunlrl",
|
|
|
|
|
|
|
|
|
|
/* extended m for cr logic */
|
|
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|
|
0, OP_BT_BT_BT, 19<<26 | 289<<1, "crset",
|
|
|
|
|
0, OP_BT_BT_BT, 19<<26 | 193<<1, "crclr",
|
|
|
|
|
0, OP_BT_BA_BA, 19<<26 | 449<<1, "crmove",
|
|
|
|
|
0, OP_BT_BA_BA, 19<<26 | 33<<1, "crnot",
|
|
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|
|
|
2007-11-02 18:56:58 +00:00
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|
|
/* Fixed point instructions (page 29) */
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0, OP_RT_RA_D, 34<<26, "lbz",
|
|
|
|
|
0, OP_RT_RA_RB, 31<<26 | 87<<1, "lbzx",
|
|
|
|
|
0, OP_RT_RA_D, 35<<26, "lbzu",
|
|
|
|
|
0, OP_RT_RA_RB, 31<<26 | 119<<1, "lbzux",
|
|
|
|
|
0, OP_RT_RA_D, 40<<26, "lhz",
|
|
|
|
|
0, OP_RT_RA_RB, 31<<26 | 279<<1, "lhzx",
|
|
|
|
|
0, OP_RT_RA_D, 41<<26, "lhzu",
|
|
|
|
|
0, OP_RT_RA_RB, 31<<26 | 311<<1, "lhzux",
|
|
|
|
|
0, OP_RT_RA_D, 42<<26, "lha",
|
|
|
|
|
0, OP_RT_RA_RB, 31<<26 | 343<<1, "lhax",
|
|
|
|
|
0, OP_RT_RA_D, 43<<26, "lhau",
|
|
|
|
|
0, OP_RT_RA_RB, 31<<26 | 375<<1, "lhaux",
|
|
|
|
|
0, OP_RT_RA_D, 32<<26, "lwz",
|
|
|
|
|
0, OP_RT_RA_RB, 31<<26 | 23<<1, "lwzx",
|
|
|
|
|
0, OP_RT_RA_D, 33<<26, "lwzu",
|
|
|
|
|
0, OP_RT_RA_RB, 31<<26 | 55<<1, "lwzux",
|
|
|
|
|
0, OP_RT_RA_DS, 58<<26 | 2<<0, "lwa",
|
|
|
|
|
0, OP_RT_RA_RB, 31<<26 | 341<<1, "lwax",
|
|
|
|
|
0, OP_RT_RA_RB, 31<<26 | 363<<1, "lwaux",
|
|
|
|
|
0, OP_RT_RA_DS, 58<<26, "ld",
|
|
|
|
|
0, OP_RT_RA_RB, 31<<26 | 21<<1, "ldx",
|
|
|
|
|
0, OP_RT_RA_DS, 58<<26 | 1<<0, "ldu",
|
|
|
|
|
0, OP_RT_RA_RB, 31<<26 | 53<<1, "ldux",
|
|
|
|
|
|
|
|
|
|
0, OP_RS_RA_D, 38<<26, "stb",
|
|
|
|
|
0, OP_RS_RA_RB, 31<<26 | 215<<1, "stbx",
|
|
|
|
|
0, OP_RS_RA_D, 39<<26, "stbu",
|
|
|
|
|
0, OP_RS_RA_RB, 31<<26 | 247<<1, "stbux",
|
|
|
|
|
0, OP_RS_RA_D, 44<<26, "sth",
|
|
|
|
|
0, OP_RS_RA_RB, 31<<26 | 407<<1, "sthx",
|
|
|
|
|
0, OP_RS_RA_D, 45<<26, "sthu",
|
|
|
|
|
0, OP_RS_RA_RB, 31<<26 | 439<<1, "sthux",
|
|
|
|
|
0, OP_RS_RA_D, 36<<26, "stw",
|
|
|
|
|
0, OP_RS_RA_RB, 31<<26 | 151<<1, "stwx",
|
|
|
|
|
0, OP_RS_RA_D, 37<<26, "stwu",
|
|
|
|
|
0, OP_RS_RA_RB, 31<<26 | 183<<1, "stwux",
|
|
|
|
|
0, OP_RS_RA_DS, 62<<26, "std",
|
|
|
|
|
0, OP_RS_RA_RB, 31<<26 | 149<<1, "stdx",
|
|
|
|
|
0, OP_RS_RA_DS, 62<<26 | 1<<0, "stdu",
|
|
|
|
|
0, OP_RS_RA_RB, 31<<26 | 181<<1, "stdux",
|
|
|
|
|
|
|
|
|
|
/* page 42 */
|
|
|
|
|
0, OP_RT_RA_RB, 31<<26 | 790<<1, "lhbrx",
|
|
|
|
|
0, OP_RT_RA_RB, 31<<26 | 534<<1, "lwbrx",
|
|
|
|
|
0, OP_RS_RA_RB, 31<<26 | 918<<1, "sthbrx",
|
|
|
|
|
0, OP_RS_RA_RB, 31<<26 | 662<<1, "stwbrx",
|
|
|
|
|
|
|
|
|
|
/* page 44 */
|
|
|
|
|
0, OP_RT_RA_D, 46<<26, "lmw",
|
|
|
|
|
0, OP_RS_RA_D, 47<<26, "stmw",
|
|
|
|
|
|
|
|
|
|
/* page 45 */
|
|
|
|
|
0, OP_RT_RA_NB, 31<<26 | 597<<1, "lswi",
|
|
|
|
|
0, OP_RT_RA_RB, 31<<26 | 533<<1, "lswx",
|
|
|
|
|
0, OP_RS_RA_NB, 31<<26 | 725<<1, "stswi",
|
|
|
|
|
0, OP_RS_RA_RB, 31<<26 | 661<<1, "stswx",
|
|
|
|
|
|
|
|
|
|
/* page 49 */
|
|
|
|
|
0, OP_RT_RA_SI, 14<<26, "addi",
|
|
|
|
|
0, OP_RT_RA_SI, 15<<26, "addis",
|
|
|
|
|
0, OP_RT_RA_RB_C, 31<<26 | 0<<10 | 266<<1, "add",
|
|
|
|
|
0, OP_RT_RA_RB_C, 31<<26 | 1<<10 | 266<<1, "addo",
|
|
|
|
|
0, OP_RT_RA_RB_C, 31<<26 | 0<<10 | 40<<1, "subf",
|
|
|
|
|
0, OP_RT_RA_RB_C, 31<<26 | 1<<10 | 40<<1, "subfo",
|
|
|
|
|
0, OP_RT_RA_SI_addic, 12<<26, "addic", /* special case C */
|
|
|
|
|
0, OP_RT_RA_SI, 8<<26, "subfic",
|
Teach the assembler about PowerPC extended mnemonics.
Also make a few changes to basic mnemonics. Fix typo in name of the
basic "creqv". Add the basic "addc" and relatives, because it would
be odd to have the extended "subc" without "addc". Fix the basic
"rldicl", "rldicr", "rldic", "rldimi" to correctly encode the 6-bit MB
field. Fix "slw" and relatives to correctly swap their RA and RS
operands.
Add many, but not all, of the extended mnemonics from IBM's Power ISA
Version 2.06 Book I Appendix E. (I used 2.06, published 2009, just
because I already had the PDF of it.) This commit includes mnemonics
for branching, subtraction, traps, bit rotation, and a few others,
like "mflr" and "nop". The assembler now understands branches like
`beq cr7, label` and bit shifts like `slwi r7, r7, 2`. These encode
the same machine instructions as the basic "bc" and "rlwinm".
Some operands to basic names become optional. The assembler no longer
requires the level in "sc" or the branch hint in "bcctr" and "bclr";
they default to zero. Some extended names take an optional branch
hint or condition register.
Some extended names are still missing. I don't provide names with
static branch prediction, like "beq+" or "bge-", because the assembler
parses '+' and '-' as operators, not as part of an instruction name.
I also don't provide some names that 2.06 has for moving to or from
the condition register or some special purpose registers, names like
"mtcr" or "mfuamr".
This commit also deletes some unused tokens and one unused yacc rule.
2017-01-22 04:49:29 +00:00
|
|
|
0, OP_RT_RA_RB_C, 31<<26 | 0<<10 | 10<<1, "addc",
|
|
|
|
|
0, OP_RT_RA_RB_C, 31<<26 | 1<<10 | 10<<1, "addco",
|
|
|
|
|
0, OP_RT_RA_RB_C, 31<<26 | 0<<10 | 8<<1, "subfc",
|
|
|
|
|
0, OP_RT_RA_RB_C, 31<<26 | 1<<10 | 8<<1, "subfco",
|
2007-11-02 18:56:58 +00:00
|
|
|
0, OP_RT_RA_RB_C, 31<<26 | 0<<10 | 138<<1, "adde",
|
|
|
|
|
0, OP_RT_RA_RB_C, 31<<26 | 1<<10 | 138<<1, "addeo",
|
|
|
|
|
0, OP_RT_RA_RB_C, 31<<26 | 0<<10 | 136<<1, "subfe",
|
|
|
|
|
0, OP_RT_RA_RB_C, 31<<26 | 1<<10 | 136<<1, "subfeo",
|
|
|
|
|
0, OP_RT_RA_C, 31<<26 | 0<<10 | 234<<1, "addme",
|
|
|
|
|
0, OP_RT_RA_C, 31<<26 | 1<<10 | 234<<1, "addmeo",
|
|
|
|
|
0, OP_RT_RA_C, 31<<26 | 0<<10 | 232<<1, "subfme",
|
|
|
|
|
0, OP_RT_RA_C, 31<<26 | 1<<10 | 232<<1, "subfmeo",
|
|
|
|
|
0, OP_RT_RA_C, 31<<26 | 0<<10 | 202<<1, "addze",
|
|
|
|
|
0, OP_RT_RA_C, 31<<26 | 1<<10 | 202<<1, "addzeo",
|
|
|
|
|
0, OP_RT_RA_C, 31<<26 | 0<<10 | 200<<1, "subfze",
|
|
|
|
|
0, OP_RT_RA_C, 31<<26 | 1<<10 | 200<<1, "subfzeo",
|
|
|
|
|
0, OP_RT_RA_C, 31<<26 | 0<<10 | 104<<1, "neg",
|
|
|
|
|
0, OP_RT_RA_C, 31<<26 | 1<<10 | 104<<1, "nego",
|
|
|
|
|
|
Teach the assembler about PowerPC extended mnemonics.
Also make a few changes to basic mnemonics. Fix typo in name of the
basic "creqv". Add the basic "addc" and relatives, because it would
be odd to have the extended "subc" without "addc". Fix the basic
"rldicl", "rldicr", "rldic", "rldimi" to correctly encode the 6-bit MB
field. Fix "slw" and relatives to correctly swap their RA and RS
operands.
Add many, but not all, of the extended mnemonics from IBM's Power ISA
Version 2.06 Book I Appendix E. (I used 2.06, published 2009, just
because I already had the PDF of it.) This commit includes mnemonics
for branching, subtraction, traps, bit rotation, and a few others,
like "mflr" and "nop". The assembler now understands branches like
`beq cr7, label` and bit shifts like `slwi r7, r7, 2`. These encode
the same machine instructions as the basic "bc" and "rlwinm".
Some operands to basic names become optional. The assembler no longer
requires the level in "sc" or the branch hint in "bcctr" and "bclr";
they default to zero. Some extended names take an optional branch
hint or condition register.
Some extended names are still missing. I don't provide names with
static branch prediction, like "beq+" or "bge-", because the assembler
parses '+' and '-' as operators, not as part of an instruction name.
I also don't provide some names that 2.06 has for moving to or from
the condition register or some special purpose registers, names like
"mtcr" or "mfuamr".
This commit also deletes some unused tokens and one unused yacc rule.
2017-01-22 04:49:29 +00:00
|
|
|
/* extended m for addition */
|
|
|
|
|
0, OP_RT_RA_D, 14<<26, "la",
|
|
|
|
|
0, OP_RT_SI, 14<<26 | 0<<16, "li",
|
|
|
|
|
0, OP_RT_SI, 15<<26 | 0<<16, "lis",
|
|
|
|
|
|
|
|
|
|
/* extended m for subtraction */
|
|
|
|
|
0, OP_RT_RB_RA_C, 31<<26 | 0<<10 | 40<<1, "sub",
|
|
|
|
|
0, OP_RT_RB_RA_C, 31<<26 | 1<<10 | 40<<1, "subo",
|
|
|
|
|
0, OP_RT_RB_RA_C, 31<<26 | 0<<10 | 8<<1, "subc",
|
|
|
|
|
0, OP_RT_RB_RA_C, 31<<26 | 0<<10 | 8<<1, "subco",
|
|
|
|
|
0, OP_RT_RA_SI_subi, 14<<26, "subi",
|
|
|
|
|
0, OP_RT_RA_SI_subi, 15<<26, "subis",
|
|
|
|
|
0, OP_RT_RA_SI_subic, 12<<26, "subic",
|
|
|
|
|
|
2007-11-02 18:56:58 +00:00
|
|
|
/* page 54 */
|
|
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|
0, OP_RT_RA_SI, 7<<26, "mulli",
|
|
|
|
|
0, OP_RT_RA_RB_C, 31<<26 | 0<<10 | 233<<1, "mulld",
|
|
|
|
|
0, OP_RT_RA_RB_C, 31<<26 | 1<<10 | 233<<1, "mulldo",
|
|
|
|
|
0, OP_RT_RA_RB_C, 31<<26 | 0<<10 | 235<<1, "mullw",
|
|
|
|
|
0, OP_RT_RA_RB_C, 31<<26 | 1<<10 | 235<<1, "mullwo",
|
|
|
|
|
0, OP_RT_RA_RB_C, 31<<26 | 73<<1, "mulhd",
|
|
|
|
|
0, OP_RT_RA_RB_C, 31<<26 | 75<<1, "mulhw",
|
|
|
|
|
0, OP_RT_RA_RB_C, 31<<26 | 9<<1, "mulhdu",
|
|
|
|
|
0, OP_RT_RA_RB_C, 31<<26 | 11<<1, "mulhwu",
|
|
|
|
|
|
|
|
|
|
/* page 56 */
|
|
|
|
|
0, OP_RT_RA_RB_C, 31<<26 | 0<<10 | 489<<1, "divd",
|
|
|
|
|
0, OP_RT_RA_RB_C, 31<<26 | 1<<10 | 489<<1, "divdo",
|
|
|
|
|
0, OP_RT_RA_RB_C, 31<<26 | 0<<10 | 491<<1, "divw",
|
|
|
|
|
0, OP_RT_RA_RB_C, 31<<26 | 1<<10 | 491<<1, "divwo",
|
|
|
|
|
0, OP_RT_RA_RB_C, 31<<26 | 0<<10 | 457<<1, "divdu",
|
|
|
|
|
0, OP_RT_RA_RB_C, 31<<26 | 1<<10 | 457<<1, "divduo",
|
|
|
|
|
0, OP_RT_RA_RB_C, 31<<26 | 0<<10 | 459<<1, "divwu",
|
|
|
|
|
0, OP_RT_RA_RB_C, 31<<26 | 1<<10 | 459<<1, "divwuo",
|
|
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|
|
|
|
|
|
|
/* page 58 */
|
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0, OP_BF_L_RA_SI, 11<<26, "cmpi",
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|
0, OP_BF_L_RA_RB, 31<<26 | 0<<1, "cmp",
|
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|
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|
0, OP_BF_L_RA_UI, 10<<26, "cmpli",
|
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|
|
|
0, OP_BF_L_RA_RB, 31<<26 | 32<<1, "cmpl",
|
|
|
|
|
|
Teach the assembler about PowerPC extended mnemonics.
Also make a few changes to basic mnemonics. Fix typo in name of the
basic "creqv". Add the basic "addc" and relatives, because it would
be odd to have the extended "subc" without "addc". Fix the basic
"rldicl", "rldicr", "rldic", "rldimi" to correctly encode the 6-bit MB
field. Fix "slw" and relatives to correctly swap their RA and RS
operands.
Add many, but not all, of the extended mnemonics from IBM's Power ISA
Version 2.06 Book I Appendix E. (I used 2.06, published 2009, just
because I already had the PDF of it.) This commit includes mnemonics
for branching, subtraction, traps, bit rotation, and a few others,
like "mflr" and "nop". The assembler now understands branches like
`beq cr7, label` and bit shifts like `slwi r7, r7, 2`. These encode
the same machine instructions as the basic "bc" and "rlwinm".
Some operands to basic names become optional. The assembler no longer
requires the level in "sc" or the branch hint in "bcctr" and "bclr";
they default to zero. Some extended names take an optional branch
hint or condition register.
Some extended names are still missing. I don't provide names with
static branch prediction, like "beq+" or "bge-", because the assembler
parses '+' and '-' as operators, not as part of an instruction name.
I also don't provide some names that 2.06 has for moving to or from
the condition register or some special purpose registers, names like
"mtcr" or "mfuamr".
This commit also deletes some unused tokens and one unused yacc rule.
2017-01-22 04:49:29 +00:00
|
|
|
/* extended m for comparison */
|
|
|
|
|
0, OP_BF_RA_SI, 11<<26 | 1<<21, "cmpdi",
|
|
|
|
|
0, OP_BF_RA_RB, 31<<26 | 1<<21 | 0<<1, "cmpd",
|
|
|
|
|
0, OP_BF_RA_UI, 10<<26 | 1<<21, "cmpldi",
|
|
|
|
|
0, OP_BF_RA_RB, 31<<26 | 1<<21 | 32<<1, "cmpld",
|
|
|
|
|
0, OP_BF_RA_SI, 11<<26 | 0<<21, "cmpwi",
|
|
|
|
|
0, OP_BF_RA_RB, 31<<26 | 0<<21 | 0<<1, "cmpw",
|
|
|
|
|
0, OP_BF_RA_UI, 10<<26 | 0<<21, "cmplwi",
|
|
|
|
|
0, OP_BF_RA_RB, 31<<26 | 0<<21 | 32<<1, "cmplw",
|
|
|
|
|
|
2007-11-02 18:56:58 +00:00
|
|
|
/* page 60 */
|
|
|
|
|
0, OP_TO_RA_SI, 2<<26, "tdi",
|
|
|
|
|
0, OP_TO_RA_SI, 3<<26, "twi",
|
|
|
|
|
0, OP_TO_RA_RB, 31<<26 | 68<<1, "td",
|
|
|
|
|
0, OP_TO_RA_RB, 31<<26 | 4<<1, "tw",
|
|
|
|
|
|
Teach the assembler about PowerPC extended mnemonics.
Also make a few changes to basic mnemonics. Fix typo in name of the
basic "creqv". Add the basic "addc" and relatives, because it would
be odd to have the extended "subc" without "addc". Fix the basic
"rldicl", "rldicr", "rldic", "rldimi" to correctly encode the 6-bit MB
field. Fix "slw" and relatives to correctly swap their RA and RS
operands.
Add many, but not all, of the extended mnemonics from IBM's Power ISA
Version 2.06 Book I Appendix E. (I used 2.06, published 2009, just
because I already had the PDF of it.) This commit includes mnemonics
for branching, subtraction, traps, bit rotation, and a few others,
like "mflr" and "nop". The assembler now understands branches like
`beq cr7, label` and bit shifts like `slwi r7, r7, 2`. These encode
the same machine instructions as the basic "bc" and "rlwinm".
Some operands to basic names become optional. The assembler no longer
requires the level in "sc" or the branch hint in "bcctr" and "bclr";
they default to zero. Some extended names take an optional branch
hint or condition register.
Some extended names are still missing. I don't provide names with
static branch prediction, like "beq+" or "bge-", because the assembler
parses '+' and '-' as operators, not as part of an instruction name.
I also don't provide some names that 2.06 has for moving to or from
the condition register or some special purpose registers, names like
"mtcr" or "mfuamr".
This commit also deletes some unused tokens and one unused yacc rule.
2017-01-22 04:49:29 +00:00
|
|
|
/* extended m for traps */
|
|
|
|
|
0, OP_TOX_RA_RB, 31<<26 | 4<<21 | 68<<1, "tdeq",
|
|
|
|
|
0, OP_TOX_RA_SI, 2<<26 | 4<<21, "tdeqi",
|
|
|
|
|
0, OP_TOX_RA_RB, 31<<26 | 12<<21 | 68<<1, "tdge",
|
|
|
|
|
0, OP_TOX_RA_SI, 2<<26 | 12<<21, "tdgei",
|
|
|
|
|
0, OP_TOX_RA_RB, 31<<26 | 8<<21 | 68<<1, "tdgt",
|
|
|
|
|
0, OP_TOX_RA_SI, 2<<26 | 8<<21, "tdgti",
|
|
|
|
|
0, OP_TOX_RA_RB, 31<<26 | 20<<21 | 68<<1, "tdle",
|
|
|
|
|
0, OP_TOX_RA_SI, 2<<26 | 20<<21, "tdlei",
|
|
|
|
|
0, OP_TOX_RA_RB, 31<<26 | 5<<21 | 68<<1, "tdlge",
|
|
|
|
|
0, OP_TOX_RA_SI, 2<<26 | 5<<21, "tdlgei",
|
|
|
|
|
0, OP_TOX_RA_RB, 31<<26 | 1<<21 | 68<<1, "tdlgt",
|
|
|
|
|
0, OP_TOX_RA_SI, 2<<26 | 1<<21, "tdlgti",
|
|
|
|
|
0, OP_TOX_RA_RB, 31<<26 | 6<<21 | 68<<1, "tdlle",
|
|
|
|
|
0, OP_TOX_RA_SI, 2<<26 | 6<<21, "tdllei",
|
|
|
|
|
0, OP_TOX_RA_RB, 31<<26 | 2<<21 | 68<<1, "tdllt",
|
|
|
|
|
0, OP_TOX_RA_SI, 2<<26 | 2<<21, "tdllti",
|
|
|
|
|
0, OP_TOX_RA_RB, 31<<26 | 6<<21 | 68<<1, "tdlng",
|
|
|
|
|
0, OP_TOX_RA_SI, 2<<26 | 6<<21, "tdlngi",
|
|
|
|
|
0, OP_TOX_RA_RB, 31<<26 | 5<<21 | 68<<1, "tdlnl",
|
|
|
|
|
0, OP_TOX_RA_SI, 2<<26 | 5<<21, "tdlnli",
|
|
|
|
|
0, OP_TOX_RA_RB, 31<<26 | 16<<21 | 68<<1, "tdlt",
|
|
|
|
|
0, OP_TOX_RA_SI, 2<<26 | 16<<21, "tdlti",
|
|
|
|
|
0, OP_TOX_RA_RB, 31<<26 | 24<<21 | 68<<1, "tdne",
|
|
|
|
|
0, OP_TOX_RA_SI, 2<<26 | 24<<21, "tdnei",
|
|
|
|
|
0, OP_TOX_RA_RB, 31<<26 | 20<<21 | 68<<1, "tdng",
|
|
|
|
|
0, OP_TOX_RA_SI, 2<<26 | 20<<21, "tdngi",
|
|
|
|
|
0, OP_TOX_RA_RB, 31<<26 | 12<<21 | 68<<1, "tdnl",
|
|
|
|
|
0, OP_TOX_RA_SI, 2<<26 | 12<<21, "tdnli",
|
|
|
|
|
0, OP_TOX_RA_RB, 31<<26 | 31<<21 | 68<<1, "tdu",
|
|
|
|
|
0, OP_TOX_RA_SI, 2<<26 | 31<<21, "tdui",
|
|
|
|
|
0, OP, 31<<26 | 31<<21 | 4<<1, "trap",
|
|
|
|
|
0, OP_TOX_RA_RB, 31<<26 | 4<<21 | 4<<1, "tweq",
|
|
|
|
|
0, OP_TOX_RA_SI, 3<<26 | 4<<21, "tweqi",
|
|
|
|
|
0, OP_TOX_RA_RB, 31<<26 | 12<<21 | 4<<1, "twge",
|
|
|
|
|
0, OP_TOX_RA_SI, 3<<26 | 12<<21, "twgei",
|
|
|
|
|
0, OP_TOX_RA_RB, 31<<26 | 8<<21 | 4<<1, "twgt",
|
|
|
|
|
0, OP_TOX_RA_SI, 3<<26 | 8<<21, "twgti",
|
|
|
|
|
0, OP_TOX_RA_RB, 31<<26 | 20<<21 | 4<<1, "twle",
|
|
|
|
|
0, OP_TOX_RA_SI, 3<<26 | 20<<21, "twlei",
|
|
|
|
|
0, OP_TOX_RA_RB, 31<<26 | 5<<21 | 4<<1, "twlge",
|
|
|
|
|
0, OP_TOX_RA_SI, 3<<26 | 5<<21, "twlgei",
|
|
|
|
|
0, OP_TOX_RA_RB, 31<<26 | 1<<21 | 4<<1, "twlgt",
|
|
|
|
|
0, OP_TOX_RA_SI, 3<<26 | 1<<21, "twlgti",
|
|
|
|
|
0, OP_TOX_RA_RB, 31<<26 | 6<<21 | 4<<1, "twlle",
|
|
|
|
|
0, OP_TOX_RA_SI, 3<<26 | 6<<21, "twllei",
|
|
|
|
|
0, OP_TOX_RA_RB, 31<<26 | 2<<21 | 4<<1, "twllt",
|
|
|
|
|
0, OP_TOX_RA_SI, 3<<26 | 2<<21, "twllti",
|
|
|
|
|
0, OP_TOX_RA_RB, 31<<26 | 6<<21 | 4<<1, "twlng",
|
|
|
|
|
0, OP_TOX_RA_SI, 3<<26 | 6<<21, "twlngi",
|
|
|
|
|
0, OP_TOX_RA_RB, 31<<26 | 5<<21 | 4<<1, "twlnl",
|
|
|
|
|
0, OP_TOX_RA_SI, 3<<26 | 5<<21, "twlnli",
|
|
|
|
|
0, OP_TOX_RA_RB, 31<<26 | 16<<21 | 4<<1, "twlt",
|
|
|
|
|
0, OP_TOX_RA_SI, 3<<26 | 16<<21, "twlti",
|
|
|
|
|
0, OP_TOX_RA_RB, 31<<26 | 24<<21 | 4<<1, "twne",
|
|
|
|
|
0, OP_TOX_RA_SI, 3<<26 | 24<<21, "twnei",
|
|
|
|
|
0, OP_TOX_RA_RB, 31<<26 | 20<<21 | 4<<1, "twng",
|
|
|
|
|
0, OP_TOX_RA_SI, 3<<26 | 20<<21, "twngi",
|
|
|
|
|
0, OP_TOX_RA_RB, 31<<26 | 12<<21 | 4<<1, "twnl",
|
|
|
|
|
0, OP_TOX_RA_SI, 3<<26 | 12<<21, "twnli",
|
|
|
|
|
0, OP_TOX_RA_RB, 31<<26 | 31<<21 | 4<<1, "twu",
|
|
|
|
|
0, OP_TOX_RA_SI, 3<<26 | 31<<21, "twui",
|
|
|
|
|
|
2007-11-02 18:56:58 +00:00
|
|
|
/* page 62 */
|
|
|
|
|
0, OP_RS_RA_UI_CC, 28<<26, "andi", /* C compulsory */
|
|
|
|
|
0, OP_RS_RA_UI_CC, 29<<26, "andis", /* C compulsory */
|
|
|
|
|
0, OP_RS_RA_UI, 24<<26, "ori",
|
|
|
|
|
0, OP_RS_RA_UI, 25<<26, "oris",
|
|
|
|
|
0, OP_RS_RA_UI, 26<<26, "xori",
|
|
|
|
|
0, OP_RS_RA_UI, 27<<26, "xoris",
|
|
|
|
|
0, OP_RS_RA_RB_C, 31<<26 | 28<<1, "and",
|
|
|
|
|
0, OP_RS_RA_RB_C, 31<<26 | 444<<1, "or",
|
|
|
|
|
0, OP_RS_RA_RB_C, 31<<26 | 316<<1, "xor",
|
|
|
|
|
0, OP_RS_RA_RB_C, 31<<26 | 476<<1, "nand",
|
|
|
|
|
0, OP_RS_RA_RB_C, 31<<26 | 124<<1, "nor",
|
|
|
|
|
0, OP_RS_RA_RB_C, 31<<26 | 284<<1, "eqv",
|
|
|
|
|
0, OP_RS_RA_RB_C, 31<<26 | 60<<1, "andc",
|
|
|
|
|
0, OP_RS_RA_RB_C, 31<<26 | 412<<1, "orc",
|
|
|
|
|
0, OP_RS_RA_C, 31<<26 | 954<<1, "extsb",
|
|
|
|
|
0, OP_RS_RA_C, 31<<26 | 922<<1, "extsh",
|
|
|
|
|
0, OP_RS_RA_C, 31<<26 | 986<<1, "extsw",
|
|
|
|
|
0, OP_RS_RA_C, 31<<26 | 58<<1, "cntlzd",
|
|
|
|
|
0, OP_RS_RA_C, 31<<26 | 26<<1, "cntlzw",
|
|
|
|
|
|
Teach the assembler about PowerPC extended mnemonics.
Also make a few changes to basic mnemonics. Fix typo in name of the
basic "creqv". Add the basic "addc" and relatives, because it would
be odd to have the extended "subc" without "addc". Fix the basic
"rldicl", "rldicr", "rldic", "rldimi" to correctly encode the 6-bit MB
field. Fix "slw" and relatives to correctly swap their RA and RS
operands.
Add many, but not all, of the extended mnemonics from IBM's Power ISA
Version 2.06 Book I Appendix E. (I used 2.06, published 2009, just
because I already had the PDF of it.) This commit includes mnemonics
for branching, subtraction, traps, bit rotation, and a few others,
like "mflr" and "nop". The assembler now understands branches like
`beq cr7, label` and bit shifts like `slwi r7, r7, 2`. These encode
the same machine instructions as the basic "bc" and "rlwinm".
Some operands to basic names become optional. The assembler no longer
requires the level in "sc" or the branch hint in "bcctr" and "bclr";
they default to zero. Some extended names take an optional branch
hint or condition register.
Some extended names are still missing. I don't provide names with
static branch prediction, like "beq+" or "bge-", because the assembler
parses '+' and '-' as operators, not as part of an instruction name.
I also don't provide some names that 2.06 has for moving to or from
the condition register or some special purpose registers, names like
"mtcr" or "mfuamr".
This commit also deletes some unused tokens and one unused yacc rule.
2017-01-22 04:49:29 +00:00
|
|
|
/* extended m using logic */
|
|
|
|
|
0, OP_RS_RA_RA_C, 31<<26 | 444<<1, "mr",
|
|
|
|
|
0, OP, 24<<26, "nop",
|
|
|
|
|
0, OP_RS_RA_RA_C, 31<<26 | 124<<1, "not",
|
|
|
|
|
0, OP, 26<<26, "xnop",
|
|
|
|
|
|
2007-11-02 18:56:58 +00:00
|
|
|
/* page 69 */
|
Teach the assembler about PowerPC extended mnemonics.
Also make a few changes to basic mnemonics. Fix typo in name of the
basic "creqv". Add the basic "addc" and relatives, because it would
be odd to have the extended "subc" without "addc". Fix the basic
"rldicl", "rldicr", "rldic", "rldimi" to correctly encode the 6-bit MB
field. Fix "slw" and relatives to correctly swap their RA and RS
operands.
Add many, but not all, of the extended mnemonics from IBM's Power ISA
Version 2.06 Book I Appendix E. (I used 2.06, published 2009, just
because I already had the PDF of it.) This commit includes mnemonics
for branching, subtraction, traps, bit rotation, and a few others,
like "mflr" and "nop". The assembler now understands branches like
`beq cr7, label` and bit shifts like `slwi r7, r7, 2`. These encode
the same machine instructions as the basic "bc" and "rlwinm".
Some operands to basic names become optional. The assembler no longer
requires the level in "sc" or the branch hint in "bcctr" and "bclr";
they default to zero. Some extended names take an optional branch
hint or condition register.
Some extended names are still missing. I don't provide names with
static branch prediction, like "beq+" or "bge-", because the assembler
parses '+' and '-' as operators, not as part of an instruction name.
I also don't provide some names that 2.06 has for moving to or from
the condition register or some special purpose registers, names like
"mtcr" or "mfuamr".
This commit also deletes some unused tokens and one unused yacc rule.
2017-01-22 04:49:29 +00:00
|
|
|
0, OP_RA_RS_SH6_MB6_C, 30<<26 | 0<<2, "rldicl",
|
|
|
|
|
0, OP_RA_RS_SH6_MB6_C, 30<<26 | 1<<2, "rldicr",
|
|
|
|
|
0, OP_RA_RS_SH6_MB6_C, 30<<26 | 2<<2, "rldic",
|
|
|
|
|
0, OP_RA_RS_SH5_MB5_ME5_C, 21<<26, "rlwinm",
|
|
|
|
|
0, OP_RA_RS_RB_MB6_C, 30<<26 | 8<<1, "rldcl",
|
|
|
|
|
0, OP_RA_RS_RB_MB6_C, 30<<26 | 9<<1, "rldcr",
|
|
|
|
|
0, OP_RA_RS_RB_MB5_ME5_C, 23<<26, "rlwnm",
|
|
|
|
|
0, OP_RA_RS_SH6_MB6_C, 30<<26 | 3<<2, "rldimi",
|
|
|
|
|
0, OP_RA_RS_SH5_MB5_ME5_C, 20<<26, "rlwimi",
|
|
|
|
|
|
|
|
|
|
/* extended m for doubleword rotation */
|
|
|
|
|
0, OP_clrlsldi, 30<<26 | 2<<2, "clrlsldi",
|
|
|
|
|
0, OP_clrldi, 30<<26 | 0<<2, "clrldi",
|
|
|
|
|
0, OP_clrrdi, 30<<26 | 1<<2, "clrrdi",
|
|
|
|
|
0, OP_extldi, 30<<26 | 0<<2, "extldi",
|
|
|
|
|
0, OP_extrdi, 30<<26 | 1<<2, "extrdi",
|
|
|
|
|
0, OP_insrdi, 30<<26 | 3<<2, "insrdi",
|
|
|
|
|
0, OP_RA_RS_RB_C, 30<<26 | MB6(0) | 8<<1, "rotld",
|
|
|
|
|
0, OP_RA_RS_SH6_C, 30<<26 | MB6(0) | 0<<2, "rotldi",
|
|
|
|
|
0, OP_rotrdi, 30<<26 | 0<<2, "rotrdi",
|
|
|
|
|
0, OP_sldi, 30<<26 | 1<<2, "sldi",
|
|
|
|
|
0, OP_srdi, 30<<26 | 0<<2, "srdi",
|
|
|
|
|
|
|
|
|
|
/* extended m for word rotation */
|
|
|
|
|
0, OP_clrlslwi, 21<<26, "clrlslwi",
|
|
|
|
|
0, OP_clrlwi, 21<<26, "clrlwi",
|
|
|
|
|
0, OP_clrrwi, 21<<26, "clrrwi",
|
|
|
|
|
0, OP_extlwi, 21<<26, "extlwi",
|
|
|
|
|
0, OP_extrwi, 21<<26, "extrwi",
|
|
|
|
|
0, OP_inslwi, 20<<26, "inslwi",
|
|
|
|
|
0, OP_insrwi, 20<<26, "insrwi",
|
|
|
|
|
0, OP_RA_RS_RB_C, 23<<26 | 0<<6 | 31<<1, "rotlw",
|
|
|
|
|
0, OP_RA_RS_SH5_C, 21<<26 | 0<<6 | 31<<1, "rotlwi",
|
|
|
|
|
0, OP_rotrwi, 21<<26, "rotrwi",
|
|
|
|
|
0, OP_slwi, 21<<26, "slwi",
|
|
|
|
|
0, OP_srwi, 21<<26, "srwi",
|
2007-11-02 18:56:58 +00:00
|
|
|
|
|
|
|
|
/* page 74 */
|
Teach the assembler about PowerPC extended mnemonics.
Also make a few changes to basic mnemonics. Fix typo in name of the
basic "creqv". Add the basic "addc" and relatives, because it would
be odd to have the extended "subc" without "addc". Fix the basic
"rldicl", "rldicr", "rldic", "rldimi" to correctly encode the 6-bit MB
field. Fix "slw" and relatives to correctly swap their RA and RS
operands.
Add many, but not all, of the extended mnemonics from IBM's Power ISA
Version 2.06 Book I Appendix E. (I used 2.06, published 2009, just
because I already had the PDF of it.) This commit includes mnemonics
for branching, subtraction, traps, bit rotation, and a few others,
like "mflr" and "nop". The assembler now understands branches like
`beq cr7, label` and bit shifts like `slwi r7, r7, 2`. These encode
the same machine instructions as the basic "bc" and "rlwinm".
Some operands to basic names become optional. The assembler no longer
requires the level in "sc" or the branch hint in "bcctr" and "bclr";
they default to zero. Some extended names take an optional branch
hint or condition register.
Some extended names are still missing. I don't provide names with
static branch prediction, like "beq+" or "bge-", because the assembler
parses '+' and '-' as operators, not as part of an instruction name.
I also don't provide some names that 2.06 has for moving to or from
the condition register or some special purpose registers, names like
"mtcr" or "mfuamr".
This commit also deletes some unused tokens and one unused yacc rule.
2017-01-22 04:49:29 +00:00
|
|
|
0, OP_RA_RS_RB_C, 31<<26 | 27<<1, "sld",
|
|
|
|
|
0, OP_RA_RS_RB_C, 31<<26 | 24<<1, "slw",
|
|
|
|
|
0, OP_RA_RS_RB_C, 31<<26 | 539<<1, "srd",
|
|
|
|
|
0, OP_RA_RS_RB_C, 31<<26 | 536<<1, "srw",
|
|
|
|
|
0, OP_RA_RS_SH6_C, 31<<26 | 413<<2, "sradi",
|
|
|
|
|
0, OP_RA_RS_SH5_C, 31<<26 | 824<<1, "srawi",
|
|
|
|
|
0, OP_RA_RS_RB_C, 31<<26 | 794<<1, "srad",
|
|
|
|
|
0, OP_RA_RS_RB_C, 31<<26 | 792<<1, "sraw",
|
2007-11-02 18:56:58 +00:00
|
|
|
|
|
|
|
|
/* page 78 */
|
|
|
|
|
0, OP_RS_SPR, 31<<26 | 467<<1, "mtspr",
|
|
|
|
|
0, OP_RT_SPR, 31<<26 | 339<<1, "mfspr",
|
|
|
|
|
0, OP_RS_FXM, 31<<26 | 0<<21 | 144<<1, "mtcrf",
|
|
|
|
|
0, OP_RT, 31<<26 | 0<<21 | 19<<1, "mfcr",
|
|
|
|
|
|
Teach the assembler about PowerPC extended mnemonics.
Also make a few changes to basic mnemonics. Fix typo in name of the
basic "creqv". Add the basic "addc" and relatives, because it would
be odd to have the extended "subc" without "addc". Fix the basic
"rldicl", "rldicr", "rldic", "rldimi" to correctly encode the 6-bit MB
field. Fix "slw" and relatives to correctly swap their RA and RS
operands.
Add many, but not all, of the extended mnemonics from IBM's Power ISA
Version 2.06 Book I Appendix E. (I used 2.06, published 2009, just
because I already had the PDF of it.) This commit includes mnemonics
for branching, subtraction, traps, bit rotation, and a few others,
like "mflr" and "nop". The assembler now understands branches like
`beq cr7, label` and bit shifts like `slwi r7, r7, 2`. These encode
the same machine instructions as the basic "bc" and "rlwinm".
Some operands to basic names become optional. The assembler no longer
requires the level in "sc" or the branch hint in "bcctr" and "bclr";
they default to zero. Some extended names take an optional branch
hint or condition register.
Some extended names are still missing. I don't provide names with
static branch prediction, like "beq+" or "bge-", because the assembler
parses '+' and '-' as operators, not as part of an instruction name.
I also don't provide some names that 2.06 has for moving to or from
the condition register or some special purpose registers, names like
"mtcr" or "mfuamr".
This commit also deletes some unused tokens and one unused yacc rule.
2017-01-22 04:49:29 +00:00
|
|
|
/* extended m for special purpose registers */
|
|
|
|
|
0, OP_RT, 31<<26 | 9<<16 | 0<<11 | 339<<1, "mfctr",
|
|
|
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|
0, OP_RT, 31<<26 | 8<<16 | 0<<11 | 339<<1, "mflr",
|
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|
0, OP_RT, 31<<26 | 1<<16 | 0<<11 | 339<<1, "mfxer",
|
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|
0, OP_RT, 31<<26 | 9<<16 | 0<<11 | 467<<1, "mtctr",
|
|
|
|
|
0, OP_RT, 31<<26 | 8<<16 | 0<<11 | 467<<1, "mtlr",
|
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|
0, OP_RT, 31<<26 | 1<<16 | 0<<11 | 467<<1, "mtxer",
|
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|
|
|
2007-11-02 18:56:58 +00:00
|
|
|
/* Floating point instructions (page 83) */
|
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|
|
0, OP_FRT_RA_D, 48<<26, "lfs",
|
|
|
|
|
0, OP_FRT_RA_RB, 31<<26 | 535<<1, "lfsx",
|
|
|
|
|
0, OP_FRT_RA_D, 49<<26, "lfsu",
|
|
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|
|
0, OP_FRT_RA_RB, 31<<26 | 567<<1, "lfsux",
|
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|
|
0, OP_FRT_RA_D, 50<<26, "lfd",
|
|
|
|
|
0, OP_FRT_RA_RB, 31<<26 | 599<<1, "lfdx",
|
|
|
|
|
0, OP_FRT_RA_D, 51<<26, "lfdu",
|
|
|
|
|
0, OP_FRT_RA_RB, 31<<26 | 631<<1, "lfdux",
|
|
|
|
|
0, OP_FRS_RA_D, 52<<26, "stfs",
|
|
|
|
|
0, OP_FRS_RA_RB, 31<<26 | 663<<1, "stfsx",
|
|
|
|
|
0, OP_FRS_RA_D, 53<<26, "stfsu",
|
|
|
|
|
0, OP_FRS_RA_RB, 31<<26 | 695<<1, "stfsux",
|
|
|
|
|
0, OP_FRS_RA_D, 54<<26, "stfd",
|
|
|
|
|
0, OP_FRS_RA_RB, 31<<26 | 727<<1, "stfdx",
|
|
|
|
|
0, OP_FRS_RA_D, 55<<26, "stfdu",
|
|
|
|
|
0, OP_FRS_RA_RB, 31<<26 | 759<<1, "stfdux",
|
|
|
|
|
0, OP_FRS_RA_RB, 31<<26 | 983<<1, "stfiwx",
|
|
|
|
|
|
|
|
|
|
0, OP_FRT_FRB_C, 63<<26 | 72<<1, "fmr",
|
|
|
|
|
0, OP_FRT_FRB_C, 63<<26 | 40<<1, "fneg",
|
|
|
|
|
0, OP_FRT_FRB_C, 63<<26 | 264<<1, "fabs",
|
|
|
|
|
0, OP_FRT_FRB_C, 63<<26 | 136<<1, "fnabs",
|
|
|
|
|
|
|
|
|
|
0, OP_FRT_FRA_FRB_C, 63<<26 | 21<<1, "fadd",
|
|
|
|
|
0, OP_FRT_FRA_FRB_C, 59<<26 | 21<<1, "fadds",
|
|
|
|
|
0, OP_FRT_FRA_FRB_C, 63<<26 | 20<<1, "fsub",
|
|
|
|
|
0, OP_FRT_FRA_FRB_C, 59<<26 | 20<<1, "fsubs",
|
|
|
|
|
0, OP_FRT_FRA_FRC_C, 63<<26 | 25<<1, "fmul",
|
|
|
|
|
0, OP_FRT_FRA_FRC_C, 59<<26 | 25<<1, "fmuls",
|
|
|
|
|
0, OP_FRT_FRA_FRB_C, 63<<26 | 18<<1, "fdiv",
|
|
|
|
|
0, OP_FRT_FRA_FRB_C, 59<<26 | 18<<1, "fdivs",
|
|
|
|
|
|
|
|
|
|
0, OP_FRT_FRA_FRC_FRB_C, 63<<26 | 29<<1, "fmadd",
|
|
|
|
|
0, OP_FRT_FRA_FRC_FRB_C, 59<<26 | 29<<1, "fmadds",
|
|
|
|
|
0, OP_FRT_FRA_FRC_FRB_C, 63<<26 | 28<<1, "fmsub",
|
|
|
|
|
0, OP_FRT_FRA_FRC_FRB_C, 59<<26 | 28<<1, "fmsubs",
|
|
|
|
|
0, OP_FRT_FRA_FRC_FRB_C, 63<<26 | 31<<1, "fnmadd",
|
|
|
|
|
0, OP_FRT_FRA_FRC_FRB_C, 59<<26 | 31<<1, "fnmadds",
|
|
|
|
|
0, OP_FRT_FRA_FRC_FRB_C, 63<<26 | 30<<1, "fnmsub",
|
|
|
|
|
0, OP_FRT_FRA_FRC_FRB_C, 59<<26 | 30<<1, "fnmsubs",
|
|
|
|
|
|
|
|
|
|
0, OP_FRT_FRB_C, 63<<26 | 12<<1, "frsp",
|
|
|
|
|
0, OP_FRT_FRB_C, 63<<26 | 814<<1, "fctid",
|
|
|
|
|
0, OP_FRT_FRB_C, 63<<26 | 815<<1, "fctidz",
|
|
|
|
|
0, OP_FRT_FRB_C, 63<<26 | 14<<1, "fctiw",
|
|
|
|
|
0, OP_FRT_FRB_C, 63<<26 | 15<<1, "fctiwz",
|
|
|
|
|
0, OP_FRT_FRB_C, 63<<26 | 846<<1, "fcfid",
|
|
|
|
|
|
|
|
|
|
0, OP_BF_FRA_FRB, 63<<26 | 0<<1, "fcmpu",
|
|
|
|
|
0, OP_BF_FRA_FRB, 63<<26 | 32<<1, "fcmpo",
|
|
|
|
|
|
|
|
|
|
0, OP_FRT_C, 63<<26 | 583<<1, "mffs",
|
|
|
|
|
0, OP_BF_BFA, 63<<26 | 64<<1, "mcrfs",
|
|
|
|
|
0, OP_BF_U_C, 63<<26 | 134<<1, "mtfsfi",
|
|
|
|
|
0, OP_FLM_FRB_C, 63<<26 | 711<<1, "mtfsf",
|
|
|
|
|
0, OP_BT_C, 63<<26 | 70<<1, "mtfsb0",
|
|
|
|
|
0, OP_BT_C, 63<<26 | 38<<1, "mtfsb1",
|
|
|
|
|
|
|
|
|
|
0, OP_FRT_FRB_C, 63<<26 | 22<<1, "fsqrt",
|
|
|
|
|
0, OP_FRT_FRB_C, 59<<26 | 22<<1, "fsqrts",
|
|
|
|
|
0, OP_FRT_FRB_C, 59<<26 | 24<<1, "fres",
|
|
|
|
|
0, OP_FRT_FRB_C, 63<<26 | 26<<1, "frsqrte",
|
|
|
|
|
0, OP_FRT_FRA_FRC_FRB_C, 63<<26 | 23<<1, "fsel",
|
|
|
|
|
|
|
|
|
|
/* page 98 */
|
