1987-03-02 11:28:52 +00:00
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.\" $Header$
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1991-10-01 12:18:39 +00:00
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.TH M68K2_AS 6 "$Revision$"
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1987-03-02 11:28:52 +00:00
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.ad
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.SH NAME
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m68k2_as \- assembler for Motorola 68000
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.SH SYNOPSIS
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1991-10-01 12:18:39 +00:00
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~em/lib.bin/m68k2/as [options] argument ...
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1987-03-02 11:28:52 +00:00
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.SH DESCRIPTION
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This assembler is made with the general framework
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described in \fIuni_ass\fP(6). It is an assembler generating relocatable
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object code in \fIack.out\fP(5) format.
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.SH SYNTAX
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.IP registers
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The 68000 has the following registers:
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seven data-registers (d1 - d7), seven address-registers (a1 - a6, sp)
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of which sp is the system stack pointer, a program counter (pc),
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a status register (sr), and a condition codes register (ccr) which is actually
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just the low order byte of the status register.
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.IP "addressing modes"
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.nf
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.ta 8n 16n 24n 32n 40n 48n
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syntax meaning (name)
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reg contents of \fIreg\fP is operand, where \fIreg\fP is
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one of the registers mentioned above (register direct)
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(areg) contents of \fIareg\fP is address of operand, where
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\fIareg\fP is an address-register
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(address register indirect)
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(areg)+ same as (areg), but after the address is used,
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\fIareg\fP is incremented by the operand length
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(postincrement)
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-(areg) same as (areg), but before the address is used,
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\fIareg\fP is decremented by the operand length
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(predecrement)
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expr(areg)
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expr(pc) \fIexpr\fP + the contents of the register yields the
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address of the operand (displacement)
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expr(areg, ireg)
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expr(pc, ireg) \fIexpr\fP + the contents of the register + the contents
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of \fIireg\fP yields the address of the operand. \fIireg\fP is
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an address- or a data-register.
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\fIireg\fP may be followed by .w or .l indicating whether
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the size of the index is a word or a long
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(displacement with index)
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expr \fIexpr\fP is the address of the operand
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(absolute address)
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#expr \fIexpr\fP is the operand (immediate)
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.fi
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Some instructions have as operand a register list. This list consists of
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one or more ranges of registers separated by '/'s. A register range consists
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of either one register (e.g. d3) or two registers separated by a '-'
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(e.g. a2-a4, or d4-d5). The two registers must be in the same set (address-
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or data-registers) and the first must have a lower number than the second.
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.IP instructions
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Some instructions can have a byte, word, or longword operand.
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This may be indicated by prepending the mnemonic with .b, .w, or .l
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respectively. Default is .w.
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.SH "SEE ALSO"
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uni_ass(6),
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ack(1),
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ack.out(5),
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.br
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MC68000 16-bit microprocessor User's manual, Motorola Inc, 1979
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.SH EXAMPLE
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.sp 2
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.nf
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.ta 8n 16n 24n 32n 40n 48n 56n 64n
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.define .cii
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.sect .text
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.cii:
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movem.l a0/d0/d1,.savreg
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move.l (sp)+,a0 ! return address
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move (sp)+,d0 ! destination size
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sub (sp)+,d0 ! destination - source size
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bgt 1f
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sub d0,sp ! pop extra bytes
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bra 3f
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1:
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move (sp),d1
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ext.l d1
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swap d1
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asr #1,d0
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2:
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move.w d1,-(sp)
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sub #1,d0
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bgt 2b
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3:
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move.l a0,-(sp)
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movem.l .savreg,a0/d0/d1
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rts
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.fi
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