Major bugfix where instructions weren't being shrunk correctly. (Turns out there's built-in support for doing this, which I hadn't found.)
--HG-- branch : dtrg-videocore
This commit is contained in:
David Given
parent
b6680a48cc
commit
3b07fee160
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@ -10,7 +10,7 @@
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#define ALWAYS 14
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extern void alu_instr_reg(quad opcode, int cc, int rd, int ra, int rb);
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extern void alu_instr_lit(quad opcode, int cc, int rd, int ra, quad value);
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extern void alu_instr_lit(quad opcode, int cc, int rd, int ra, long value);
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extern void misc_instr_reg(quad opcode, int cc, int rd, int ra, int rb);
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extern void misc_instr_lit(quad opcode, int cc, int rd, int ra, quad value);
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extern void branch_instr(int bl, int cc, struct expr_t* expr);
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@ -34,12 +34,12 @@ void alu_instr_reg(quad op, int cc, int rd, int ra, int rb)
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/* Assemble an ALU instruction where rb is a literal. */
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void alu_instr_lit(quad op, int cc, int rd, int ra, quad value)
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void alu_instr_lit(quad op, int cc, int rd, int ra, long value)
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{
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/* 16 bit short form? */
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if ((cc == ALWAYS) && !(op & 1) && (value <= 0x1f) && (ra == rd) &&
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(ra < 0x10))
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if ((cc == ALWAYS) && !(op & 1) && (value >= 0) && (value <= 0x1f) &&
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(ra == rd) && (ra < 0x10))
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{
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emit2(B16(01100000,00000000) | (op<<8) | (value<<4) | (rd<<0));
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return;
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@ -47,7 +47,7 @@ void alu_instr_lit(quad op, int cc, int rd, int ra, quad value)
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/* 32 bit medium form? */
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if (value <= 0x1f)
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if ((value >= 0) && (value <= 0x1f))
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{
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emit2(B16(11000000,00000000) | (op<<5) | (rd<<0));
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emit2(B16(00000000,01000000) | (ra<<11) | (cc<<7) | (value<<0));
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@ -99,6 +99,7 @@ void branch_instr(int bl, int cc, struct expr_t* expr)
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{
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quad pc = DOTVAL;
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quad type = expr->typ & S_TYP;
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int d;
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/* Sanity checking. */
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@ -107,71 +108,52 @@ void branch_instr(int bl, int cc, struct expr_t* expr)
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if (type == S_ABS)
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serror("can't use absolute addresses here");
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switch (pass)
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/* The VC4 branch instructions express distance in 2-byte
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* words. */
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d = (int32_t)expr->val - (int32_t)pc;
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if ((pass == 2) && (d > 0) && !(expr->typ & S_DOT))
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d -= DOTGAIN;
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d /= 2;
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/* If this is a reference to code within this section, and it's
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* close enough to the program counter, we can use a short-
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* form instruction. */
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if (small(!bl && (type == DOTTYP) && fitx(d, 7), 2))
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{
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emit2(B16(00011000,00000000) | (cc<<7) | (d&0x7f));
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return;
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}
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/* Absolute addresses and references to other sections
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* need the full 32 bits. */
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newrelo(expr->typ, RELOVC4|RELPC);
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if (bl)
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{
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case 0:
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/* Calculate size of instructions only. For now we just assume
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* that they're going to be the maximum size, 32 bits. */
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quad v, hiv, lov;
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emit4(0);
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break;
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if (!fitx(d, 27))
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toobig();
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case 1:
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case 2:
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{
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/* The VC4 branch instructions express distance in 2-byte
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* words. */
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v = maskx(d, 27);
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hiv = v >> 23;
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lov = v & 0x007fffff;
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emit2(B16(10010000,10000000) | (lov>>16) | (hiv<<8));
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emit2(B16(00000000,00000000) | (lov&0xffff));
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}
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else
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{
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quad v;
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int d = ((int32_t)expr->val - (int32_t)pc) / 2;
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if (!fitx(d, 23))
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toobig();
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/* We now know the worst case for the instruction layout. At
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* this point we can emit the instructions, which may shrink
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* the code. */
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if (!bl && (type == DOTTYP))
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{
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/* This is a reference to code within this section. If it's
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* close enough to the program counter, we can use a short-
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* form instruction. */
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if (fitx(d, 7))
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{
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emit2(B16(00011000,00000000) | (cc<<7) | (d&0x7f));
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break;
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}
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}
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/* Absolute addresses and references to other sections
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* need the full 32 bits. */
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newrelo(expr->typ, RELOVC4|RELPC);
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if (bl)
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{
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quad v, hiv, lov;
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if (!fitx(d, 27))
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toobig();
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v = maskx(d, 27);
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hiv = v >> 23;
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lov = v & 0x007fffff;
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emit2(B16(10010000,10000000) | (lov>>16) | (hiv<<8));
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emit2(B16(00000000,00000000) | (lov&0xffff));
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}
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else
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{
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quad v;
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if (!fitx(d, 23))
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toobig();
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v = maskx(d, 23);
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emit2(B16(10010000,00000000) | (cc<<8) | (v>>16));
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emit2(B16(00000000,00000000) | (v&0xffff));
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}
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break;
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}
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v = maskx(d, 23);
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emit2(B16(10010000,00000000) | (cc<<8) | (v>>16));
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emit2(B16(00000000,00000000) | (v&0xffff));
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}
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}
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@ -352,66 +334,45 @@ void mem_postincr_instr(quad opcode, int cc, int rd, int rs)
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void mem_address_instr(quad opcode, int rd, struct expr_t* expr)
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{
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static const char sizes[] = {4, 2, 1, 2};
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static const char sizes[] = {4, 4, 2, 2, 1, 1, 2, 2};
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int size = sizes[opcode];
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quad type = expr->typ & S_TYP;
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int d, scaledd;
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/* Sanity checking. */
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if (type == S_ABS)
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serror("can't use absolute addresses here");
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switch (pass)
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d = expr->val - DOTVAL;
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if ((pass == 2) && (d > 0) && !(expr->typ & S_DOT))
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d -= DOTGAIN;
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scaledd = d/size;
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/* If this is a reference to an address within this section, and
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* it's close enough to the program counter, we can use a
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* shorter instruction. */
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if (small((type==DOTTYP) && fitx(scaledd, 16), 2))
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{
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case 0:
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/* Calculate size of instructions only. For now we just assume
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* that they're going to be the maximum size, 48 bits. */
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emit2(B16(10101010,00000000) | (opcode<<5) | (rd<<0));
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emit2(scaledd);
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return;
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}
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emit2(0);
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emit4(0);
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break;
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/* Otherwise we need the full 48 bits. */
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case 1:
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case 2:
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{
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int d = expr->val - DOTVAL;
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newrelo(expr->typ, RELOVC4|RELPC);
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/* We now know the worst case for the instruction layout. At
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* this point we can emit the instructions, which may shrink
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* the code. */
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/* VC4 relocations store the PC-relative delta into the
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* destination section in the instruction data. The linker will
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* massage this, and scale it appropriately. */
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if (type == DOTTYP)
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{
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int scaledd = d/size;
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if (!fitx(d, 27))
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toobig();
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/* This is a reference to an address within this section. If
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* it's close enough to the program counter, we can use a
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* shorter instruction. */
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if (fitx(scaledd, 16))
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{
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emit2(B16(10101010,00000000) | (opcode<<5) | (rd<<0));
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emit2(scaledd);
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return;
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}
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}
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/* Otherwise we need the full 48 bits. */
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newrelo(expr->typ, RELOVC4|RELPC);
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/* VC4 relocations store the PC-relative delta into the
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* destination section in the instruction data. The linker will
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* massage this, and scale it appropriately. */
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if (!fitx(d, 27))
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toobig();
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emit2(B16(11100111,00000000) | (opcode<<5) | (rd<<0));
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emit4((31<<27) | maskx(d, 27));
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break;
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}
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}
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emit2(B16(11100111,00000000) | (opcode<<5) | (rd<<0));
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emit4((31<<27) | maskx(d, 27));
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}
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/* Common code for handling addcmp: merge in as much of expr as will fit to
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@ -420,33 +381,23 @@ void mem_address_instr(quad opcode, int rd, struct expr_t* expr)
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static void branch_addcmp_common(quad opcode, int bits, struct expr_t* expr)
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{
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quad type = expr->typ & S_TYP;
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int d;
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switch (pass)
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{
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case 0:
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/* Calculate size of instructions only. */
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if (type != DOTTYP)
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serror("can't use this type of branch to jump outside the section");
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emit2(0);
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break;
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/* The VC4 branch instructions express distance in 2-byte
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* words. */
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case 1:
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case 2:
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{
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if (type != DOTTYP)
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serror("can't use this type of branch to jump outside the section");
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d = (expr->val - DOTVAL-2 + 4);
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if ((pass == 2) && (d > 0) && !(expr->typ & S_DOT))
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d -= DOTGAIN;
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d /= 2;
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/* The VC4 branch instructions express distance in 2-byte
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* words. */
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if (!fitx(d, bits))
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serror("target of branch is too far away");
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int d = (expr->val - DOTVAL-2 + 4) / 2;
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if (!fitx(d, bits))
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serror("target of branch is too far away");
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emit2(opcode | maskx(d, bits));
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break;
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}
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}
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emit2(opcode | maskx(d, bits));
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}
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void branch_addcmp_reg_reg_instr(int cc, int rd, int ra, int rs, struct expr_t* expr)
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@ -518,6 +469,10 @@ void lea_address_instr(int rd, struct expr_t* expr)
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{
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quad pc = DOTVAL;
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quad type = expr->typ & S_TYP;
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int d = expr->val - pc;
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if ((pass == 2) && (d > 0) && !(expr->typ & S_DOT))
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d -= DOTGAIN;
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if (type == S_ABS)
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serror("can't use absolute addresses here");
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