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Fix an incorrect instruction, and incredibly broken li handling.

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This commit is contained in:
David Given 2018-09-12 23:59:09 +02:00
parent ecb3395aba
commit 57338b1991
2 changed files with 7 additions and 5 deletions
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4
mach/mips/as/instructions.dat
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@ -234,8 +234,8 @@
010011<RS-><RT->00000<FD->001101 "suxc1" FD=fpr ',' RT=gpr '(' RS=gpr ')'
111001<RS-><FT-><IMM-----------> "swc1" FT=fpr ',' IMM=e16 '(' RS=gpr ')'
010011<RS-><RT->00000<FD->001000 "swxc1" FD=fpr ',' RT=gpr '(' RS=gpr ')'
010001<F-->00000<FS-><FD->001001 "trunc" ".l" F=fmt FS=fpr ',' FD=fpr
010001<F-->00000<FS-><FD->001101 "trunc" ".w" F=fmt FS=fpr ',' FD=fpr
010001<F-->00000<FS-><FD->001001 "trunc" ".l" F=fmt FD=fpr ',' FS=fpr
010001<F-->00000<FS-><FD->001101 "trunc" ".w" F=fmt FD=fpr ',' FS=fpr
# Generic coprocessor instructions.

8
mach/mips/as/mach4.c
View file

@ -2,10 +2,12 @@
| OP_LI GPR ',' extabsexp
{
word_t reg = $2;
word_t val = $4;
uint32_t val = $4;
if ((val < -0x8000) || (val > 0xffff))
if (((int32_t)val >= -0x8000) && ((int32_t)val <= 0x7fff))
emit4(0x24000000 | (reg<<16) | (val & 0xffff)); /* addiu reg, zero, value */
else if (val <= 0xffff)
emit4(0x34000000 | (reg<<16) | val); /* ori reg, zero, value */
else
{
emit4(0x3c000000 | (reg<<16) | (val>>16)); /* lui reg, value */
@ -16,7 +18,7 @@
{
word_t reg = $2;
word_t type = $4.typ & S_TYP;
word_t val = $4.val;
uint32_t val = $4.val;
if (type != S_ABS)
newrelo($4.typ, RELO2HI | FIXUPFLAGS);