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65
man/6500_as.1
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man/6500_as.1
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\" $Header$
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.TH 6500_AS 1
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.ad
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.SH NAME
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6500_as \- assembler for Mostek 6500
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.SH SYNOPSIS
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/usr/em/lib/6500_as [options] argument ...
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.SH DESCRIPTION
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This assembler is made with the general framework
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described in \fIuni_ass\fP(6).
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.SH "SEGMENTS and TYPES"
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An additional segment, the \fIzeropage\fP, can be started by the
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\&\fI.zero\fP pseudo-instruction.
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Some adressing-modes require an address between 0 and 255.
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Such an address must be defined with the means of the \fI.zero\fP
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pseudo-instruction.
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A plain number between 0 and 255 is not allowed.
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The assembler will complain that it must be a zero page expression.
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.IP example
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\&.zero
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.br
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answer: .space 1
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.br
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\&.text
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.br
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and (answer, x)
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.SH SYNTAX
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.IP expressions
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An two-byte expression followed by the pseudo-operator \fI.h\fP (\fI.l\fP)
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has the value of the higher (lower) byte of the expression.
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\&\fI.h\fP and \fI.l\fP bind stronger than all other operators.
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E.g. -1.h parses as -[1.h] which has value 0.
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You have to write [-1].h to get 0xFF.
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.IP "addressing modes"
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.nf
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.ta 8 16 24 32 40 48
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syntax meaning (name)
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#expr 8-bit value (immediate)
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expr address (direct)
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expr, x expr + contents of x
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or or
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expr, y expr + contents of y
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yields address (indexed)
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(expr) address of address (only with JMP) (indirect)
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In the next two addressing modes `expr' has to be
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a zeropage expression.
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(expr, x) expr + contents of x
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yields address (pre-indexed indirect)
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(expr), y contents of expr + contents of y
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yields address (post-indexed indirect)
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.fi
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.IP instructions
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There are two mnemonics that do not map onto one machine-instruction:
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`add' and `sub'. `Add mode' maps onto `clc; adc mode'.
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`Sub mode' maps onto `sec; sbc mode'.
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.SH "SEE ALSO"
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uni_ass(6),
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ack(1)
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55
man/6800_as.1
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55
man/6800_as.1
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\" $Header$
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.TH 6800_AS 1
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.ad
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.SH NAME
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6800_as \- assembler for Motorola 6800
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.SH SYNOPSIS
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/usr/em/lib/6800_as [options] argument ...
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.SH DESCRIPTION
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This assembler is made with the general framework
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described in \fIuni_ass\fP(6).
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.SH SYNTAX
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.IP registers
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The 6800 has two accumulator registers, A and B. An instruction that refers
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to accumulator A, has an "a" as last character. In the same way a "b" means
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that the instruction uses B as accumulator.
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.IP "addressing modes"
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.nf
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.ta 8 16 24 32 40 48
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syntax meaning (name)
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#expr with cpx, ldx, lds a 2-byte value,
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otherwise a 1-byte value (immediate)
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<expr 1-byte address. Not allowed with:
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asl, asr, clr, com, dec, inc, lsl, lsr,
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neg, rol, ror, tst (base page direct)
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expr 2-byte address (extended direct)
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expr, x 1-byte expr + contents of x
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yields address (indexed)
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.fi
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.SH "SEE ALSO"
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uni_ass(6),
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ack(1),
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.br
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A. Osborne, 6800 programming for logic design,
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Adam Osborne and Associates Inc., 1977
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.SH EXAMPLE
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An example of Motorola 6800 assembly code.
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.sp 2
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.nf
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.ta 8 16 32 40 48 56 64
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.data
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val: 0
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.text
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ldx <val
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com val, x
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bhs someplace ! branch on carry clear
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sta <val
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adda #18 ! add 18 to accumulator A
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.fi
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.SH BUGS
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You have to specify whether an address fits in one byte
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with the token `<'. It should be done automatically.
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36
man/8080_as.1
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36
man/8080_as.1
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@ -0,0 +1,36 @@
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\" $Header$
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.TH 8080_AS 1
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.ad
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.SH NAME
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8080_as \- assembler for Intel 8080 and 8085
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.SH SYNOPSIS
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/usr/em/lib/8080_as [options] argument ...
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.SH DESCRIPTION
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This assembler is made with the general framework
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described in \fIuni_ass\fP(6).
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.SH SYNTAX
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.IP registers
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The 8080 has seven one-byte registers: a, b, c, d, e, h, l;
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and two two-byte registers: sp and psw, respectively the stack pointer
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and the processor status word.
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.IP "addressing modes"
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.nf
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.ta 8 16 24 32 40 48
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syntax meaning
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expr one- or two-byte address or immediate
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data, depending on the instruction.
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a,b,c,d,e,h,l
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sp,psw (lower byte) of register
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b,d,h register-pair b-c, d-e, or h-l
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m register-pair h-l is address of
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(one or two byte) operand
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.fi
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.SH "SEE ALSO"
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uni_ass(1),
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ack(1),
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.br
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System 80/20-4 microcomputer hardware reference manual, 1978 Intel corporation
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