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This commit is contained in:
ceriel 1989-02-08 14:57:48 +00:00
parent fb88f5dbdd
commit f682c264a8
10 changed files with 2007 additions and 0 deletions
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7
mach/i386/ce/.distr Normal file
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EM_table
Makefile
as.c
as.h
as_table
mach.c
mach.h

1104
mach/i386/ce/EM_table Normal file
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26
mach/i386/ce/Makefile Normal file
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EMHOME = ../../..
CEG = $(EMHOME)/lib/ceg/util
VERSION = make_obj
all:
make -f $(CEG)/$(VERSION)
install:
make -f $(CEG)/$(VERSION) install
cmp:
-make -f $(CEG)/$(VERSION) cmp
pr:
@pr Makefile EM_table mach.h mach.c as_table as.h as.c
opr:
make pr | opr
# total cleanup
clean:
make -f $(CEG)/$(VERSION) clean
# only remove ce, ceg, and back directories
dclean:
make -f $(CEG)/$(VERSION) dclean

362
mach/i386/ce/as.c Normal file
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#include "arg_type.h"
#include "as.h"
#define last( s) ( s + strlen( s) - 1)
#define LEFT '('
#define RIGHT ')'
#define DOLLAR '$'
block_assemble( instr, nr, first, Last)
char **instr;
int nr, first, Last;
{
int i;
/*
if ( first) {
if( strncmp( instr[0], "pop", 3) == 0) {
*instr[0] = 'P';
*( instr[0]+1) = 'O';
*( instr[0]+2) = 'P';
}
else
@clean_push_buf();
}
if ( Last && strncmp( instr[nr-1], "push", 4) == 0) {
*instr[nr-1] = 'P';
*( instr[nr-1]+1) = 'U';
*( instr[nr-1]+2) = 'S';
*( instr[nr-1]+3) = 'H';
}
*/
for( i=0; i<nr; i++)
assemble( instr[i]);
}
process_label( l)
char *l;
{
}
process_mnemonic( m)
char *m;
{
}
process_operand( str, op)
char *str;
struct t_operand *op;
/* expr -> IS_DATA en IS_LABEL
* reg -> IS_REG en IS_ACCU
* (expr) -> IS_ADDR
* expr(reg) -> IS_MEM
*/
{
char *ptr, *index();
op->type = UNKNOWN;
if ( *last( str) == RIGHT) {
ptr = index( str, LEFT);
*last( str) = '\0';
*ptr = '\0';
if ( is_reg( ptr+1, op)) {
op->type = IS_MEM;
op->expr = ( *str == '\0' ? "0" : str);
}
else {
set_label( ptr+1, op);
op->type = IS_ADDR;
}
}
else
if ( is_reg( str, op))
op->type = IS_REG;
else {
if ( contains_label( str))
set_label( str, op);
else {
op->type = IS_DATA;
op->expr = str;
}
}
}
static struct regnam {
char *regstr;
int regval;
} regnam[] = {
{ "eax", 0 },
{ "ebx", 3 },
{ "ecx", 1 },
{ "edx", 2 },
{ "esp", 4 },
{ "ebp", 5 },
{ "esi", 6 },
{ "edi", 7 },
{ "al", 0 },
{ "bl", 3 },
{ "cl", 1 },
{ "dl", 2 },
{ "ah", 4 },
{ "bh", 7 },
{ "ch", 5 },
{ "dh", 6 },
{ 0, 0}
}
;
int is_reg( str, op)
char *str;
struct t_operand *op;
{
register struct regnam *p = regnam;
while (p->regstr) {
if (! strcmp(p->regstr, str)) {
op->reg = p->regval;
return TRUE;
}
p++;
}
return FALSE;
}
#include <ctype.h>
#define isletter( c) ( isalpha( c) || c == '_')
int contains_label( str)
char *str;
{
while( !isletter( *str) && *str != '\0')
if ( *str == '$')
if ( arg_type( str) == STRING)
return( TRUE);
else
str += 2;
else
str++;
return( isletter( *str));
}
set_label( str, op)
char *str;
struct t_operand *op;
{
char *ptr, *index(), *sprint();
static char buf[256];
ptr = index( str, '+');
if ( ptr == 0)
op->off = "0";
else {
*ptr = '\0';
op->off = ptr + 1;
}
if ( isdigit( *str) && ( *(str+1) == 'b' || *(str+1) == 'f') &&
*(str+2) == '\0') {
*(str+1) = '\0'; /* remove b or f! */
op->lab = str;
op->type = IS_ILB;
}
else {
op->type = IS_LABEL;
if ( index( str, DOLLAR) != 0)
op->lab = str;
else
op->lab = sprint( buf, "\"%s\"", str);
}
}
/******************************************************************************/
mod_RM( reg, op)
int reg;
struct t_operand *op;
{
if ( REG( op))
R233( 0x3, reg, op->reg);
else if ( ADDR( op)) {
R233( 0x0, reg, 0x5);
@reloc4( %$(op->lab), %$(op->off), ABSOLUTE);
}
else if ( strcmp( op->expr, "0") == 0)
switch( op->reg) {
case AX:
case BX:
case CX:
case DX:
case DI:
case SI: R233( 0x0, reg, op->reg);
break;
case BP : R233( 0x1, reg, 0x6); /* Exception! */
@text1( 0);
break;
default : fprint( STDERR, "Wrong index register %d\n",
op->reg);
}
else {
if (isdigit(op->expr[0])) {
long l, atol();
l = atol(op->expr);
if ( l <= 127 && l >= -128) {
switch( op->reg) {
case AX:
case BX:
case CX:
case DX:
case DI:
case BP:
case SI : R233( 0x1, reg, op->reg);
break;
default : fprint( STDERR, "Wrong index register %d\n",
op->reg);
}
@text1( %$(op->expr));
} else {
switch( op->reg) {
case AX:
case BX:
case CX:
case DX:
case DI:
case BP:
case SI : R233( 0x2, reg, op->reg);
break;
default : fprint( STDERR, "Wrong index register %d\n",
op->reg);
}
@text4( %$(op->expr));
}
} else {
@if ( fit_byte( %$(op->expr)))
switch( op->reg) {
case AX:
case BX:
case CX:
case DX:
case DI:
case BP:
case SI : R233( 0x1, reg, op->reg);
break;
default : fprint( STDERR, "Wrong index register %d\n",
op->reg);
}
@text1( %$(op->expr));
@else
switch( op->reg) {
case AX:
case BX:
case CX:
case DX:
case DI:
case BP:
case SI : R233( 0x2, reg, op->reg);
break;
default : fprint( STDERR, "Wrong index register %d\n",
op->reg);
}
@text4( %$(op->expr));
@fi
}
}
}
mv_RG_EADDR( dst, src)
struct t_operand *dst, *src;
{
if ( REG(src) && dst->reg == src->reg)
; /* Nothing!! result of push/pop optimization */
else {
@text1( 0x8b);
mod_RM( dst->reg, src);
}
}
R233( a, b, c)
int a,b,c;
{
@text1( %d( (a << 6) | ( b << 3) | c));
}
R53( a, b)
int a,b;
{
@text1( %d( (a << 3) | b));
}
small_const(opc, src)
struct t_operand *src;
{
if (isdigit(src->expr[0])) {
long l, atol();
l = atol(src->expr);
if (l >= -128 && l <= 127) {
@text1(%d(opc|02));
@text1(%$(src->expr));
}
else {
@text1(%d(opc));
@text4(%$(src->expr));
}
}
else {
@if (fit_byte(%$(src->expr)))
@text1(%d(opc|02));
@text1(%$(src->expr));
@else
@text1(%d(opc));
@text1(%$(src->expr));
@fi
}
}
small_RMconst(opc, reg, dst, src)
struct t_operand *dst, *src;
{
if (isdigit(src->expr[0])) {
long l, atol();
l = atol(src->expr);
if (l >= -128 && l <= 127) {
@text1(%d(opc|02));
mod_RM(reg, dst);
@text1(%$(src->expr));
}
else {
@text1(%d(opc));
mod_RM(reg, dst);
@text4(%$(src->expr));
}
}
else {
@if (fit_byte(%$(src->expr)))
@text1(%d(opc|02));
mod_RM(reg, dst);
@text1(%$(src->expr));
@else
@text1(%d(opc));
mod_RM(reg, dst);
@text1(%$(src->expr));
@fi
}
}

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#define UNKNOWN 0
#define IS_REG 0x1
#define IS_ACCU 0x2
#define IS_DATA 0x4
#define IS_LABEL 0x8
#define IS_MEM 0x10
#define IS_ADDR 0x20
#define IS_ILB 0x40
#define AX 0
#define BX 3
#define CX 1
#define DX 2
#define CL 1
#define SP 4
#define BP 5
#define SI 6
#define DI 7
#define REG( op) ( op->type & IS_REG)
#define ACCU( op) ( op->type & IS_REG && op->reg == AX)
#define REG_CL( op) ( op->type & IS_REG && op->reg == CL)
#define DATA( op) ( op->type & IS_DATA)
#define lABEL( op) ( op->type & IS_LABEL)
#define ILB( op) ( op->type & IS_ILB)
/*#define MEM( op) ( op->type & IS_MEM)*/
#define ADDR( op) ( op->type & IS_ADDR)
#define EADDR( op) ( op->type & ( IS_ADDR | IS_MEM | IS_REG))
#define TRUE 1
#define FALSE 0
struct t_operand {
unsigned type;
int reg;
char *expr, *lab, *off;
};

218
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add dst:REG, src:EADDR ==> @text1( 0x3);
mod_RM( dst->reg, src).
... dst:ACCU, src:DATA ==> @text1( 0x5);
@text4( %$(src->expr)).
... dst:EADDR, src:DATA ==> small_RMconst(0x81, 0, dst, src).
and dst:REG, src:EADDR ==> @text1( 0x23);
mod_RM( dst->reg, src).
... dst:ACCU, src:DATA ==> @text1( 0x25);
@text4( %$(src->expr)).
call dst:lABEL ==> @text1( 0xe8);
@reloc4( %$(dst->lab), %$(dst->off), PC_REL).
... dst:EADDR ==> @text1( 0xff);
mod_RM( 2, dst).
cdq ==> @text1(0x99).
cmp dst:REG, src:EADDR ==> @text1( 0x3b);
mod_RM( dst->reg, src).
... dst:ACCU, src:DATA ==> @text1( 0x3d);
@text4( %$(src->expr)).
... dst:EADDR, src:DATA ==> small_RMconst(0x81, 7, dst, src).
dec dst:REG ==> R53( 9, dst->reg).
... dst:EADDR ==> @text1( 0xff);
mod_RM( 1, dst).
div divisor:EADDR ==> @text1( 0xf7);
mod_RM( 6, divisor).
enter nm:DATA, nm1:DATA ==> @text1( 0xc8);
@text2( %$(nm->expr));
@text1( %$(nm1->expr)).
idiv divisor:EADDR ==> @text1( 0xf7);
mod_RM( 7, divisor).
imul mplier:EADDR ==> @text1( 0xf7);
mod_RM( 5, mplier).
inc dst:REG ==> R53( 8, dst->reg).
... dst:EADDR ==> @text1( 0xff);
mod_RM( 0, dst).
jb dst:ILB ==> @text1( 0x72);
@text1( %dist( dst->lab)).
... dst:lABEL ==> @text1(0x0f);
@text1(0x12);
@reloc4( %$(dst->lab), %$(dst->off), PC_REL).
je dst:ILB ==> @text1( 0x74);
@text1( %dist( dst->lab)).
... dst:lABEL ==> @text1(0x0f);
@text1(0x14);
@reloc4( %$(dst->lab), %$(dst->off), PC_REL).
jg dst:ILB ==> @text1( 0x7f);
@text1( %dist( dst->lab)).
... dst:lABEL ==> @text1(0x0f);
@text1(0x1f);
@reloc4( %$(dst->lab), %$(dst->off), PC_REL).
jge dst:ILB ==> @text1( 0x7d);
@text1( %dist( dst->lab)).
... dst:lABEL ==> @text1(0x0f);
@text1(0x1d);
@reloc4( %$(dst->lab), %$(dst->off), PC_REL).
jl dst:ILB ==> @text1( 0x7c);
@text1( %dist( dst->lab)).
... dst:lABEL ==> @text1(0x0f);
@text1(0x1c);
@reloc4( %$(dst->lab), %$(dst->off), PC_REL).
jle dst:ILB ==> @text1( 0x7e);
@text1( %dist( dst->lab)).
... dst:lABEL ==> @text1(0x0f);
@text1(0x1e);
@reloc4( %$(dst->lab), %$(dst->off), PC_REL).
jmp dst:ILB ==> @text1( 0xeb);
@text1( %dist( dst->lab)).
... dst:lABEL ==> @text1( 0xe9);
@reloc4( %$(dst->lab), %$(dst->off), PC_REL).
jne dst:ILB ==> @text1( 0x75);
@text1( %dist( dst->lab)).
... dst:lABEL ==> @text1(0x0f);
@text1(0x85);
@reloc4( %$(dst->lab), %$(dst->off), PC_REL).
lea dst:REG, src:EADDR ==> @text1( 0x8d);
mod_RM( dst->reg, src).
loop dst:ILB ==> @text1( 0xe2);
@text1( %dist( dst->lab)).
mov dst:REG, src:EADDR ==> mv_RG_EADDR( dst, src).
... dst:REG, src:DATA ==> R53( 0x17, dst->reg);
@text4(%$(src->expr)).
... dst:EADDR, src:REG ==> @text1( 0x89);
mod_RM( src->reg, dst).
... dst:EADDR, src:DATA ==> @text1( 0xc7);
mod_RM( 0, dst);
@text4( %$(src->expr)).
... dst:EADDR, src:lABEL ==> @text1( 0xc7);
mod_RM( 0, dst);
@reloc4( %$(src->lab), %$(src->off), ABSOLUTE).
movb dst:EADDR, src:REG ==> @text1( 0x88);
mod_RM( src->reg, dst).
movzx dst:REG, src:EADDR ==> @text1(0x0f);
@text1(0xb7);
mod_RM(dst->reg, src).
mul mplier:EADDR ==> @text1( 0xf7);
mod_RM( 4, mplier).
neg dst:EADDR ==> @text1( 0xf7);
mod_RM( 3, dst).
not dst:EADDR ==> @text1( 0xf7);
mod_RM( 2, dst).
o16 ==> @text1(0x66).
or dst:REG, src:EADDR ==> @text1( 0x0b);
mod_RM( dst->reg, src).
pop dst:REG ==> R53( 0xb, dst->reg).
... dst:EADDR ==> @text1( 0x8f);
mod_RM( 0, dst).
/*
POP dst ==> @if ( push_waiting)
mov_instr( dst, AX_oper);
@assign( push_waiting, FALSE).
@else
pop_instr( dst).
@fi.
*/
push src:REG ==> R53( 0xa, src->reg).
... src:DATA ==> small_const(0x68, src).
... src:lABEL ==> @emit1(0x68);
@reloc4(%$(src->lab), %$(src->off), ABSOLUTE).
... src:EADDR ==> @text1( 0xff);
mod_RM( 6, src).
/*
PUSH src ==> mov_instr( AX_oper, src);
@assign( push_waiting, TRUE).
*/
ret ==> @text1( 0xc3). /* Always NEAR! */
leave ==> @text1( 0xc9). /* Always NEAR! */
rol dst:EADDR, src:REG_CL ==> @text1( 0xd3);
mod_RM( 0, dst).
ror dst:EADDR, src:REG_CL ==> @text1( 0xd3);
mod_RM( 1, dst).
sal dst:EADDR, src:REG_CL ==> @text1( 0xd3);
mod_RM( 4, dst).
sar dst:EADDR, src:REG_CL ==> @text1( 0xd3);
mod_RM( 7, dst).
... dst:EADDR, src:DATA ==> @text1( 0xc1);
mod_RM( 7, dst);
@text1(%$(src->expr)).
shl dst:EADDR, src:REG_CL ==> @text1(0xd3);
mod_RM(4, dst).
shr dst:EADDR, src:REG_CL ==> @text1( 0xd3);
mod_RM( 5, dst).
sub dst:REG, src:EADDR ==> @text1( 0x2b);
mod_RM( dst->reg, src).
... dst:EADDR, src:DATA ==> small_RMconst(0x81, 5, dst, src).
test dst:REG, src:EADDR ==> @text1( 0x85);
mod_RM( dst->reg, src).
xchg dst:EADDR, src:REG ==> @text1( 0x87);
mod_RM( src->reg, dst).
xor dst:REG, src:EADDR ==> @text1( 0x33);
mod_RM( dst->reg, src).

176
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#define CODE_EXPANDER
#include <system.h>
#include "back.h"
#include "mach.h"
#ifdef DEBUG
arg_error( s, arg)
char *s;
int arg;
{
fprint( STDERR, "arg_error %s %d\n", s, arg);
}
#endif
int push_waiting = FALSE;
int fit_byte( val)
int val;
{
return( val >= -128 && val <= 127);
}
con_float(str, argval)
char *str;
int argval;
{
#ifdef NOFLOAT
static int been_here;
if (argval != 4 && argval != 8)
arg_error("fcon", argval);
if (argval == 8)
gen4((FOUR_BYTES) 0);
gen4((FOUR_BYTES) 0);
if ( !been_here++)
{
fprint(STDERR, "Warning : dummy float-constant(s)\n");
}
#else
#define IEEEFLOAT
double f;
double atof();
int i;
int j;
double frexp();
#ifndef OWNFLOAT
int sign = 0;
int fraction[4] ;
#else OWNFLOAT
float fl;
char *p;
#endif OWNFLOAT
if (argval!= 4 && argval!= 8) {
arg_error("fcon", argval);
argval = 8;
}
f = atof(str);
if (f == 0) {
if (argval == 8) gen4((FOUR_BYTES) 0);
gen4((FOUR_BYTES) 0);
return;
}
#ifdef OWNFLOAT
if (argval == 4) {
/* careful: avoid overflow */
double ldexp();
f = frexp(f, &i);
fl = f;
fl = frexp(fl,&j);
if (i+j > 127) {
/* overflow situation */
gen1(f<0?0377:0177);
gen1(0377);
gen1(0377);
gen1(0377);
return;
}
if (i+j < -127) {
/* underflow situation */
gen1(f<0?0200:0);
gen1(0200);
gen1(0);
gen1(0);
return;
}
fl = ldexp(fl, i+j);
p = (char *) &fl;
}
else {
p = (char *) &f;
}
gen1(*p++&0377);
for (i = argval-1; i; i--) {
gen1(*p++&0377);
}
#else OWNFLOAT
f = frexp(f, &i);
if (f < 0) {
f = -f;
sign = 1;
}
while (f < 0.5) {
f += f;
i --;
}
f = 2*f - 1.0; /* hidden bit */
#ifdef IEEEFLOAT
if (argval == 4) {
#endif IEEEFLOAT
i = (i + 128) & 0377;
fraction[0] = (sign << 15) | (i << 7);
for (j = 6; j>= 0; j--) {
f *= 2;
if (f >= 1.0) {
f -= 1.0;
fraction[0] |= (1 << j);
}
}
#ifdef IEEEFLOAT
}
else {
i = (i + 1024) & 03777;
fraction[0] = (sign << 15) | (i << 4);
for (j = 3; j>= 0; j--) {
f *= 2;
if (f >= 1.0) {
fraction[0] |= (1 << j);
f -= 1.0;
}
}
}
#endif IEEEFLOAT
for (i = 1; i < argval / 2; i++) {
fraction[i] = 0;
for (j = 15; j>= 0; j--) {
f *= 2;
if (f >= 1.0) {
fraction[i] |= (1 << j);
f -= 1.0;
}
}
}
if (f >= 0.5) {
for (i = argval/2 - 1; i >= 0; i--) {
for (j = 0; j < 16; j++) {
if (fraction[i] & (1 << j)) {
fraction[i] &= ~(1 << j);
}
else {
fraction[i] |= (1 << j);
break;
}
}
if (j != 16) break;
}
}
for (i = 0; i < argval/2; i++) {
gen1((fraction[i]>>8)&0377);
gen1(fraction[i]&0377);
}
#endif OWNFLOAT
#endif
}
/* as long as we generate assembler ...
do_open(filename)
char *filename;
{
if (filename == 0 || ! sys_open(filename, OP_WRITE, &codefile))
return FALSE;
fprint( codefile, ".sect .text; .sect .rom; .sect .data; .sect .bss\n"); return TRUE;
}
*/

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#define BSS_INIT 0
#define ONE_BYTE int
#define TWO_BYTES int
#define FOUR_BYTES long
#define EM_WSIZE 4
#define EM_PSIZE 4
#define EM_BSIZE 8
#define NAME_FMT "_%s"
#define DNAM_FMT "_%s"
#define DLB_FMT "I_%ld"
#define ILB_FMT "I%03d%ld"
#define HOL_FMT "hol%d"
#define ALIGN_FMT ".align\n"
#define BYTE_FMT ".data1 %ld\n"
#define WORD_FMT ".data2 %ld\n"
#define LONG_FMT ".data4 %ld\n"
#define BSS_FMT ".space %ld\n"
#define SEGTXT_FMT ".sect .text\n"
#define SEGDAT_FMT ".sect .data\n"
#define SEGBSS_FMT ".sect .bss\n"
#define SYMBOL_DEF_FMT "%s :\n"
#define GLOBAL_FMT ".extern %s\n"
#define LOCAL_FMT ""
#define RELOC1_FMT ".data1 %s + %ld\n"
#define RELOC2_FMT ".data2 %s + %ld\n"
#define RELOC4_FMT ".data4 %s + %ld\n"
#define COMM_FMT ".comm %s,%ld\n"
#define GENLAB 'I'
#define TRUE 1
#define FALSE 0
#define clean_push_buf() if(push_waiting){text1(0x50);push_waiting=FALSE;}
#define assign( l, r) l = r
extern int push_waiting;
#ifndef DEBUG
#define arg_error(s,i)
#endif

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SUF=o
MAKEFILE=../../proto/libg/Makefile
MACHDEF="MACH=i386" "SUF=$(SUF)" "ASAR=aal"
BCDEF="PREF=bc" "SUB=" "SRC=lang/basic/lib"
install:
make -f $(MAKEFILE) $(BCDEF) $(MACHDEF) tailcp
cmp:
make -f $(MAKEFILE) $(BCDEF) $(MACHDEF) tail
-../../compare head_bc
-../../compare tail_bc
clean:
-rm -f *.old *.[ce$(SUF)] tail* head*
opr:
make pr | opr
pr:
@pr Makefile

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mach/i386/libbc/compmodule Executable file
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if ${MACH?} -I../../../h ${MACHFL?} $1 1>&2
then
echo `basename $1 $2`.o
else
exit 1
fi