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Fix assembly of bfffo d1[0:32], d3

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The assembler wrongly defined _bfexts_ and _bfffo_ with the same bits
as _bfextu_; this turned all bfexts and bfffo instructions into
bfextu.  Motorola's 68k Programmer's Reference Manual (1992) gives
different bits for bfexts, but still has wrong bits for bfffo.  Change
bfexts and bfffo to match the 68k emulators musahi, aranym, syn68k.

The bitfield width is from 1 to 32, not 0 to 31, so move the warning
from 32 to 0.  This doesn't change the warning message, so it will say
that 0 is "too big", when 0 is really too small.
This commit is contained in:
George Koehler 2019-09-24 10:44:48 -04:00
parent f0a2c84d93
commit fd27acb487
3 changed files with 11 additions and 6 deletions
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2
mach/m68020/as/mach2.c
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@ -83,6 +83,6 @@
%type <y_word> bcdx op_ea regs rrange
%type <y_word> reg sizedef sizenon creg
%type <y_word> off_width abs31 bd_areg_index
%type <y_word> off_width off31 wid31 bd_areg_index
%type <y_word> areg_index areg scale cp_cond fc mask
%type <y_word> fsize fregs fcregs frlist frrange

4
mach/m68020/as/mach3.c
View file

@ -68,8 +68,8 @@
{0, BITFIELD, 0166300, "bfclr"},
{0, BITFIELD, 0167300, "bfset"},
{0, BF_TO_D, 0164700, "bfextu"},
{0, BF_TO_D, 0164700, "bfexts"},
{0, BF_TO_D, 0164700, "bfffo"},
{0, BF_TO_D, 0165700, "bfexts"},
{0, BF_TO_D, 0166700, "bfffo"}, /* not 0164700 */
{0, BFINS, 0167700, "bfins"},
{0, SHIFT, 0160340, "asr"},

11
mach/m68020/as/mach4.c
View file

@ -225,12 +225,17 @@ creg : CREG
off_width /* note: these should be curly brackets, but that would
* leave us without brackets for expressions.
*/
: '[' abs31 ':' abs31 ']'
: '[' off31 ':' wid31 ']'
{ $$ = ($2<<6) | $4;
}
;
abs31 : DREG { $$ = 040 | $1;}
| absexp { fit(fit5($1));
off31 : DREG { $$ = 040 | $1;}
| absexp { fit(fit5($1)); /* 0 to 31 */
$$ = low5($1);
}
;
wid31 : DREG { $$ = 040 | $1;}
| absexp { fit(fit5($1) - 1); /* 1 to 32 */
$$ = low5($1);
}
;