6 commits

Author	SHA1	Message	Date
David Given	8edbff9795	Add assembler support for fixing up arbitrary oris/addi pairs of instructions; ... this should allow oris/lwz constant value loads, which will save an opcode.	2017-01-15 00:15:01 +01:00
David Given	a8c4dac67c	Merge from default (merging in George Koehler's PowerPC changes).	2016-10-29 22:40:40 +02:00
David Given	4a093b9eba	Add li and mr pseudoinstructions.	2016-10-18 00:21:32 +02:00
George Koehler	5b69777647	Rename our pseudo-opcode 'la' to 'li32'. ... GNU as has "la %r4,8(%r3)" as an alias for "addi %r4,%r3,8", meaning to load the address of the thing at 8(%r3). Our 'la', now 'li32', makes an addis/ori pair to load an immediate 32-bit value. For example, "li32 r4,23456789" loads a big number.	2016-09-18 17:03:23 -04:00
David Given	80cb6ba927	Eliminate the RELOH2 relocation, as it never worked --- the address would be ... calculated incorrectly because of overflow errors. Replace it with an extended RELOPPC relocation which understands addis/ori pairs; add an la pseudoop to the assembler which generates these and the appropriate relocation. Make good. --HG-- branch : dtrg-experimental-powerpc-branch	2016-09-17 12:43:15 +02:00
dtrg	4dd1ff6d80	Archival checkin (semi-working code).	2007-11-02 18:56:58 +00:00