Commit graph

12 commits

Author SHA1 Message Date
George Koehler b1badf1851 Add instructions like "lwarx". Extend manual.
Add more page numbers from PowerPC version 2.01.  Remove "xnop" not in
2.01, add "mtcr" from 2.01.  Add "lwarx" and the other instructions
from Book II.  I did not try all the newly added instructions, but
these seem to work: dcbt, dcbtst, icibi, isync, lwarx, stwcx., mftb,
mftbu

In man/powerpc_as.6 (not installed), add a summary of the registers
and addressing modes (like in i386_as.6), describe short forms, update
description of hi16/ha16, add CAVEATS about instructions that some
processors can't run.
2018-03-07 13:37:31 -05:00
George Koehler 48e3aab728 Swap RA and RS when assembling "and", "or", and such instructions.
They must use OP_RA_RS_RB_C instead of OP_RS_RA_RB_C.  The code
generator often sets RS and RA to the same register, so swapping them
causes no change in many programs.

I also rename OP_RS_RA_UI_CC to OP_RA_RS_UI_CC, and OP_RS_RA_C to
OP_RA_RS_C, because they already swap RA and RS.
2017-01-30 15:47:09 -05:00
George Koehler 5aa2ac2246 Teach the assembler about PowerPC extended mnemonics.
Also make a few changes to basic mnemonics.  Fix typo in name of the
basic "creqv".  Add the basic "addc" and relatives, because it would
be odd to have the extended "subc" without "addc".  Fix the basic
"rldicl", "rldicr", "rldic", "rldimi" to correctly encode the 6-bit MB
field.  Fix "slw" and relatives to correctly swap their RA and RS
operands.

Add many, but not all, of the extended mnemonics from IBM's Power ISA
Version 2.06 Book I Appendix E.  (I used 2.06, published 2009, just
because I already had the PDF of it.)  This commit includes mnemonics
for branching, subtraction, traps, bit rotation, and a few others,
like "mflr" and "nop".  The assembler now understands branches like
`beq cr7, label` and bit shifts like `slwi r7, r7, 2`.  These encode
the same machine instructions as the basic "bc" and "rlwinm".

Some operands to basic names become optional.  The assembler no longer
requires the level in "sc" or the branch hint in "bcctr" and "bclr";
they default to zero.  Some extended names take an optional branch
hint or condition register.

Some extended names are still missing.  I don't provide names with
static branch prediction, like "beq+" or "bge-", because the assembler
parses '+' and '-' as operators, not as part of an instruction name.
I also don't provide some names that 2.06 has for moving to or from
the condition register or some special purpose registers, names like
"mtcr" or "mfuamr".

This commit also deletes some unused tokens and one unused yacc rule.
2017-01-21 23:49:29 -05:00
David Given 9a346c382d Turns out Apple's hi16/ha16 exactly match my ha16/has16, so renamed
accordingly. (Memo to self: read the docs *before* doing the work.)
2017-01-15 11:59:33 +01:00
David Given f80acfe9f5 Signed vs unsigned lower halves of powerpc fixups are now handled by having two
assembler directives, ha16() and has16(), for the upper half; has16() applies
the sign adjustment. .powerpcfixup is now gone, as we generate the relocation
in ha*() instead. Add special logic to the linker for undoing and redoing the
sign adjustment when reading/writing fixups. Tests still pass.
2017-01-15 11:51:37 +01:00
David Given 3c0bc205fc Update the hi/lo syntax to be a bit more standard. 2017-01-15 10:21:02 +01:00
David Given 8edbff9795 Add assembler support for fixing up arbitrary oris/addi pairs of instructions;
this should allow oris/lwz constant value loads, which will save an opcode.
2017-01-15 00:15:01 +01:00
David Given a8c4dac67c Merge from default (merging in George Koehler's PowerPC changes). 2016-10-29 22:40:40 +02:00
David Given 4a093b9eba Add li and mr pseudoinstructions. 2016-10-18 00:21:32 +02:00
George Koehler 5b69777647 Rename our pseudo-opcode 'la' to 'li32'.
GNU as has "la %r4,8(%r3)" as an alias for "addi %r4,%r3,8", meaning
to load the address of the thing at 8(%r3).  Our 'la', now 'li32',
makes an addis/ori pair to load an immediate 32-bit value.  For
example, "li32 r4,23456789" loads a big number.
2016-09-18 17:03:23 -04:00
David Given 80cb6ba927 Eliminate the RELOH2 relocation, as it never worked --- the address would be
calculated incorrectly because of overflow errors.

Replace it with an extended RELOPPC relocation which understands addis/ori
pairs; add an la pseudoop to the assembler which generates these and the
appropriate relocation. Make good.

--HG--
branch : dtrg-experimental-powerpc-branch
2016-09-17 12:43:15 +02:00
dtrg 4dd1ff6d80 Archival checkin (semi-working code). 2007-11-02 18:56:58 +00:00