Commit graph

1768 commits

Author SHA1 Message Date
David Given
98fe70a7de Output register equality constraints work. 2016-10-14 22:17:02 +02:00
David Given
f06b51c981 Keep track of register types as well as attributes --- the type being how we
find new registers when evicting values. Input constraints work (they were
being ignored before). Various bug fixing so they actually work.
2016-10-12 22:58:46 +02:00
David Given
23c3575f0f The register allocator now makes a spirited attempt to honour register
attributes when allocating. Unfortunately, backward edges don't work (because
the limited def-use chain stuff doesn't work across basic blocks). Needs more
thought.
2016-10-09 15:09:34 +02:00
David Given
cfe5312fcc Predicates can now take numeric arguments. The PowerPC predicates have been
turned into generic ones (as they'll be useful everywhere). Node arguments for
predicates require the '%' prefix for consistency. Hex numbers are permitted.
2016-10-09 12:32:36 +02:00
David Given
2198db69b1 Instruction predicates work now. 2016-10-08 11:35:33 +02:00
George Koehler
65c2a8a0ae Remove stackadjust and stackoffset() from ncg.
This feature has never been used since its introduction, more than 3
years ago, in David Given's commit c93cb69 of May 8, 2013.  The commit
was for "PowerPC and M68K work".  I am not undoing the entire commit.
I am only removing the stackadjust and stackoffset() feature.

This commit removes the feature from my branch kernigh-linuxppc.  This
removal includes the mach/proto/ncg parts.  The default branch already
removed most of the feature, but kept the mach/proto/ncg parts.  That
removal happened in commit 81778b6 of May 13, 2013 (which was a merge;
git diff af0dede 81778b6).  The branch dtrg-experimental-powerpc
merged the default branch but without the removal.  That merge was
commit 4703db0f of Sep 15, 2016 (git diff 8c94b13 4703db0).  My branch
kernigh-linuxppc is off branch dtrg-experimental-powerpc, so I can no
longer get the removal by merging default.

David Given described the stackadjust feature in
  https://sourceforge.net/p/tack/mailman/message/30814691/

The instruction stackadjust would add a value to the offset, and the
function stackoffset() would return this offset.  One would use this
to track sp - fp, then omit the frame pointer by not keeping fp in a
register.
2016-10-07 20:52:13 -04:00
David Given
7f901aa4d0 We're not using 'allocates' any more; clean up. 2016-10-06 21:33:43 +02:00
David Given
88fb231d6e Better constraint syntax; mcgg now passes register usage information up to mcg;
mcg can track individual hop inputs and outputs (needed for live range
analysis!); the register allocator now puts the basic blocks into the right
order in preparation for live range analysis.
2016-10-05 22:56:25 +02:00
David Given
92502901a7 Better management of register data. Add struct hreg. 2016-10-05 21:00:28 +02:00
David Given
8d4186130d Oops --- hadn't updated the nts array for the new child order. 2016-10-04 21:32:28 +02:00
David Given
bd28bddb92 Massive rewrite of how emitters and the instruction selector works, after I
realised that the existing approach wasn't working. Now, hopefully, tracks the
instruction trees generated during selection properly.
2016-10-04 00:16:06 +02:00
David Given
68f98cbad7 Instruction selection now happens on a shadow tree, rather than on the IR tree
itself. Currently it's semantically the same but the implementation is cleaner.
2016-10-03 20:52:36 +02:00
David Given
288ee56203 Get quite a long way towards basic output-register equality constraints (needed
to make special nodes like NOP work properly). Realise that the way I'm dealing
with the instruction selector is all wrong; I need to physically copy chunks of
tree to give to burg (so I can terminate them correctly).
2016-10-02 23:25:54 +02:00
David Given
3aa30e50d1 Come up with a syntax for register constraints. 2016-10-02 21:51:25 +02:00
David Given
c079e97492 Perform SSA conversion of locals. Much, *much* better code now, at least
inasmuch as it looks better before register allocation. Basic blocks now know
their own successors and predecessors (after a certain point in the IR
processing).
2016-10-02 17:50:34 +02:00
David Given
21898f784a We're going to need some type inference after all, I think. Let's do a little
for now and see how it goes.
2016-10-01 19:10:22 +02:00
David Given
91e277e046 Predicates work; we now have prefers and requires clauses. Predicates must be
functions. Not convinced that semantic types are actually working --- there are
still problems with earlier statements leaving things in the wrong registers.
2016-10-01 13:56:52 +02:00
David Given
4a3a9a98dc It doesn't really make a lot of sense to have BURG nonterminal names different
to register classes, so combine them. Refactor the map code.
2016-10-01 12:17:14 +02:00
David Given
3a973a19f3 Move fatal(), warning() and aprintf() into the new data module (because they're
really useful).
2016-09-30 19:10:30 +02:00
David Given
b32883b013 More properly keep track of register classes. 2016-09-29 22:32:43 +02:00
David Given
b27758b7de Error check fragment rules which don't emit anything. 2016-09-29 22:14:11 +02:00
David Given
0d246c0d73 Much better handling of fragments (no run-time code needed to distinguish them
from registers) and better handling of individual hops within a paragraph ---
no more ghastly hacks to try and distinguish the input from the output.
2016-09-29 22:06:04 +02:00
David Given
a0131fdb47 You know what, the type inference stuff is a complete red herring. What this
actually needs is a more intelligent register allocator. So, remove the type
inference.
2016-09-29 19:58:02 +02:00
David Given
cc176e5183 Keep more data around about ir instructions. Implement a half-baked type
inference routine to propagate information about floats up the tree, so we know
whether to put floats into special registers as early as possible.
2016-09-26 22:12:46 +02:00
David Given
416b13fd76 Start factoring out the hardware op code. 2016-09-25 23:29:59 +02:00
David Given
39aa672422 Sort of keep track of registers and register classes. Start walking the
generated instruction tree --- holy cow, they look like instructions!
2016-09-25 22:17:14 +02:00
David Given
bde5792b1a Collapse several rule arrays into one; actually generate the array properly. 2016-09-25 17:14:54 +02:00
David Given
bcc74ba18d Stupid stringlist is stupid. Use a proper data structure, properly abstracted
out (so other things can use it).
2016-09-25 12:18:39 +02:00
David Given
9f78e0b36b Rethink the way patterns are mapped to rules; generate emitters (probably
badly).
2016-09-25 11:49:51 +02:00
David Given
7c028bdd45 We now record the code fragments to be emitted by each rule. 2016-09-25 00:21:46 +02:00
David Given
629e0ddfc6 Some instruction selection is now happening. 2016-09-24 22:46:08 +02:00
David Given
c8fcbe282a More grammar changes. 2016-09-24 19:03:55 +02:00
David Given
2acc4ed29d IR codes are now owned by mcgg; ir terminals are inserted into the table during
compilation (so you can refer to them).
2016-09-24 18:31:35 +02:00
David Given
1516657907 Crudely bolt on mcgg to mcg itself. 2016-09-24 17:20:40 +02:00
David Given
13132128a1 Parameters are parsed with getopt. Simplify, constify. 2016-09-24 16:59:49 +02:00
David Given
434eafd35d Change the predicate stuff to use costs instead; now you can use when clauses
on leaves. Remove an iburg premature optimisation (required for above).
2016-09-24 13:33:59 +02:00
David Given
d96ceea08a Lots of exploratory new grammar for instruction definitions and string and
fragment emission (none of which is hooked up to anything yet).
2016-09-24 13:08:17 +02:00
David Given
960259f0b0 Add support for labelled tree nodes. 2016-09-24 12:11:30 +02:00
David Given
4546dd5f22 Massive grammar overhaul and refactor. Hacked in support for predicates, where
instructions can be turned on and off based on their parameters. New lexer
using a lexer. Now quite a lot of the way towards being a real instruction
selector.
2016-09-21 00:43:10 +02:00
David Given
2183c6c622 Run through clang-format. 2016-09-20 21:00:16 +02:00
David Given
03b7202e54 Strip out surplus files. Rewrite README. 2016-09-20 20:46:45 +02:00
David Given
5cb3fbb3d3 Import iburg. 2016-09-20 20:44:51 +02:00
David Given
13c117d15d Import iburg. 2016-09-20 20:37:16 +02:00
George Koehler
9db305b338 Enable the Hall check again, and get powerpc to pass it.
Upon enabling the check, mach/powerpc/ncg/table fails to build as ncgg
gives many errors of "Previous rule impossible on empty stack".  David
Given reported this problem in 2013:
  https://sourceforge.net/p/tack/mailman/message/30814694/

Commit c93cb69 commented out the error in util/ncgg/cgg.y to disable
the Hall check.  This commit enables it again.  In ncgg, the Hall
check is checking that a rule is possible with an empty fake stack.
It would be possible if ncg can coerce the values from the real stack
to the fake stack.  The powerpc table defined coercions from STACK to
{FS, %a} and {FD, %a}, but the Hall check didn't understand the
coercions and rejected each rule "with FS" or "with FD".

This commit removes the FS and FD tokens and adds a new group of FSREG
registers for single-precision floats, while keeping FREG registers
for double precision.  The registers overlap, with each FSREG
containing one FREG, because it is the same register in PowerPC
hardware.  FS tokens become FSREG registers and FD tokens become FREG
registers.  The Hall check understands the coercions from STACK to
FSREG and FREG.  The idea to define separate but overlapping registers
comes from the PDP-11 table (mach/pdp/ncg/table).

This commit also removes F0 from the FREG group.  This is my attempt
to keep F0 off the fake stack, because one of the stacking rules uses
F0 as a scratch register (FSCRATCH).
2016-09-18 15:08:55 -04:00
George Koehler
9ec2918e14 In ncgg, increase MAXREGS from 80 to 200.
I need this to add more registers to powerpc.
2016-09-18 14:37:42 -04:00
George Koehler
ff4a7e3d2a Merge branch 'default' into kernigh-linuxppc 2016-09-17 18:15:54 -04:00
David Given
80cb6ba927 Eliminate the RELOH2 relocation, as it never worked --- the address would be
calculated incorrectly because of overflow errors.

Replace it with an extended RELOPPC relocation which understands addis/ori
pairs; add an la pseudoop to the assembler which generates these and the
appropriate relocation. Make good.

--HG--
branch : dtrg-experimental-powerpc-branch
2016-09-17 12:43:15 +02:00
David Given
4703db0fff Merge from default.
--HG--
branch : dtrg-experimental-powerpc-branch
2016-09-15 22:59:01 +02:00
George Koehler
b1d1b5e1f8 Fix bugs with memory allocation in ego.
cf/cf_loop.c and share/put.c tried to read the next pointer in an
element of a linked list after freeing the element.  ud/ud_copy.c
tried to read beyond the end of the _defs_ array: it only has
_nrexpldefs_ elements, not _nrdefs_ elements.

These bugs caused core dumps on OpenBSD.  Its malloc() put _defs_ near
the end of a page, so reading beyond the end crossed into an unmapped
page.  Its free() wrote junk bytes and changed the next pointer to
0xdfdfdfdfdfdfdfdf.
2016-09-09 23:37:43 -04:00
David Given
f67c98e239 Distributions are a pain --- let's not bother any more. Instead, we just tag
the repository and download a complete snapshot, old and ancient stuff and all.
2016-09-02 23:00:38 +02:00