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Author SHA1 Message Date
David Given 8200f041c2 Fix issue with logical operations and small signed constants which turned out 
to affect multiple platforms.
 2019-02-13 20:56:10 +01:00
David Given 79e7636537 Teach the code generator about the zero register and how to efficiently access 
the stack.
 2018-09-22 11:49:13 +02:00
David Given 985d3dc7d1 Remove some old, hopefully unused PowerPC code. Teach the code generator about 
non-volatile long registers.
 2018-09-20 23:30:38 +02:00
David Given cb20856aea A few more minor optimisations. 2018-09-20 00:39:13 +02:00
David Given ac921080b7 Fix incorrect ori encoding. 2018-09-20 00:06:26 +02:00
David Given 8fda024ec8 Remember to save longs and doubles. Yikes. 2018-09-19 00:09:50 +02:00
David Given d23d2dd1b3 Loads and stores (except longs, which are difficult) are now loaded with two 
instructions rather than three.
 2018-09-18 23:38:37 +02:00
David Given 692caa2b0a Add unsigned comparison rules. 2018-09-18 00:19:40 +02:00
David Given fe177bd688 Add specialist rules for signed integer comparisons; much better code. 2018-09-17 23:53:18 +02:00
David Given ec0891469f Array descriptor ranges are inclusive; adjust aar and the tests to check for 
this. All the tests except rotate build now!
 2018-09-17 19:34:38 +01:00
David Given f61500c51b Fix lar and sar, which were horribly, horribly broken. Add tests. 2018-09-17 18:44:17 +01:00
David Given abb7e3e105 Fix aar; add test. 2018-09-17 16:59:45 +01:00
David Given b665efca04 ACK loi 1 and sti 1 load and store unsigned bytes. I think. 2018-09-17 15:03:44 +01:00
David Given 0202ac8700 Fix bls4. 2018-09-17 12:53:27 +01:00
David Given 1e073e944a Added cms, and a test for it. 2018-09-17 12:42:10 +01:00
David Given 0b65591972 Add hacky 64-bit comparisons (used by M2). 2018-09-17 12:16:17 +01:00
David Given 15ae171aef Added a test for set. Fix mips set implementation. 2018-09-17 11:56:15 +01:00
David Given 7efb749003 Set fixes; also add discrete tests for and, ior, xor. 2018-09-14 14:13:35 +01:00
David Given 08b1e8d71b Make inn work; fix broken 64-bit loads and stores. 2018-09-14 13:48:43 +02:00
David Given 5d0876a30b Implement a working .trp. 2018-09-14 12:26:27 +02:00
David Given ba0849c87c Remove la; turns out that the assembler gets upset if you ask it to 
generate more than one fixup per instruction (I think).
 2018-09-14 11:30:15 +02:00
David Given c4e3d0903e Bugfix rck. 2018-09-14 00:38:31 +02:00
David Given 8c0b2f8aee Fix csa and csb. 2018-09-14 00:15:43 +02:00
David Given 57338b1991 Fix an incorrect instruction, and incredibly broken li handling. 2018-09-12 23:59:09 +02:00
David Given ecb3395aba Converting floats and doubles to integers now works, as much as these ever do 
on MIPS; turns out that it can't (or at least can't in qemu) reliably turn
INT_MIN from a double to an int.
 2018-09-12 23:58:48 +02:00
David Given 8105281534 Make sure li works properly when loading fixed up values which end up as 0. Use 
lui rather than li to load high values.
 2018-09-12 22:28:40 +02:00
David Given 8379969b6f Fix an unsubtle bug where subtractions were done backwards... 2018-09-11 23:16:50 +02:00
David Given 8230ec42ac Fix a subtle thinko which was causing bits 2-3 of jump targets to be reset. 2018-09-11 23:16:30 +02:00
David Given 0ce368324e Add the bitset helpers. We now have enough helpers for the tests to run (and 
massively fail).
 2018-09-10 23:37:28 +02:00
David Given 2f8fe3ce6e Do some cleanup; ha16[] and friends can now be used with li. 2018-09-10 23:37:04 +02:00
David Given 3122946a6f Replaced some incorrect hi16s with ha16s. 2018-09-10 23:21:54 +02:00
David Given 008737ed19 Added some more very untested helper functions. 2018-09-10 23:20:52 +02:00
David Given a1747ac916 Add the .dataf4 and .dataf8 directives to the assembler --- manually converting 
floats and doubles to bytes is not fun. It might even work!
 2018-09-10 22:56:18 +02:00
David Given 185e910246 Lots more untested helper functions. 2018-09-10 01:08:25 +02:00
David Given f8f6fa9fc1 Added some more incredibly untested helper functions. 2018-09-10 00:21:16 +02:00
David Given bb15c03339 Remember to preserve input registers if we're going to be reading from them 
after writing to the output register.
 2018-09-09 18:53:49 +02:00
David Given e88670dad4 Yikes! Turns out that FPU registers are only 32 bits wide, and doubles are 
stored in pairs, just like on the PowerPC!
 2018-09-09 18:25:00 +02:00
David Given 5dfef6f180 Rework relocations again: add RELO2HI and RELO2HISAD for the high two bytes of 
a word.
 2018-09-09 14:11:11 +02:00
David Given 95dd6f0141 Fix some niggling issues --- we have our first binary now! 2018-09-09 12:24:22 +02:00
David Given b3b7c684c6 Simplify MIPS relocations. Add RELS2 (for generic high-word relocations). Add 
support for MIPS branch-and-jump relocations.
 2018-09-09 12:23:59 +02:00
David Given d2a1d4dcda Added some very untested csa and csb implementations, based on the PowerPC 
ones.
 2018-09-08 23:12:57 +02:00
David Given 75308901bc Added hi[] and lo[] functions to the assembler; fix things enough that we now 
get to the point of failing to link programs.
 2018-09-08 22:42:06 +02:00
David Given 379c1a4a3c Rework floating point conversion. Bash enough of the table into workingness 
that the libraries build now.
 2018-09-08 22:06:38 +02:00
David Given d2c14ca44f Precisely one stack hreg gets allocated for each vreg/congruence group for 
eviction; this prevents us from having to worry about moving values from stack
slot to stack slot, which is hard.
 2018-09-08 18:59:55 +02:00
David Given b7a1c96986 MIPS appears to hate converting unsigneds to floats and vice versa. 2018-09-05 23:53:38 +02:00
David Given 7fbce066f8 We attempt to compile the first library function; we fail. 2018-09-05 00:13:01 +02:00
David Given 26fe3f7530 Added library skeletons. 2018-09-05 00:07:07 +02:00
David Given 26c0228b14 The examples all compile now (probably incorrectly, and the libc doesn't 
compile yet).
 2018-09-04 23:55:28 +02:00
David Given 9d80756253 Lots of assembler and rule bugfixing. 2018-09-04 23:43:24 +02:00
David Given fe5ca5a85f Added li and la instructions. 2018-09-03 22:47:41 +02:00