fd27acb487
The assembler wrongly defined _bfexts_ and _bfffo_ with the same bits as _bfextu_; this turned all bfexts and bfffo instructions into bfextu. Motorola's 68k Programmer's Reference Manual (1992) gives different bits for bfexts, but still has wrong bits for bfffo. Change bfexts and bfffo to match the 68k emulators musahi, aranym, syn68k. The bitfield width is from 1 to 32, not 0 to 31, so move the warning from 32 to 0. This doesn't change the warning message, so it will say that 0 is "too big", when 0 is really too small.
467 lines
11 KiB
C
467 lines
11 KiB
C
/* $Id$ */
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/*
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* (c) copyright 1987 by the Vrije Universiteit, Amsterdam, The Netherlands.
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* See the copyright notice in the ACK home directory, in the file "Copyright".
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*/
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/*
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* Motorola 68020 keywords
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*/
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{0, SIZE, SIZE_B, ".b"},
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{0, SIZE, SIZE_W, ".w"},
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{0, SIZE, SIZE_L, ".l"},
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{0, DREG, 00, "d0"},
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{0, DREG, 01, "d1"},
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{0, DREG, 02, "d2"},
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{0, DREG, 03, "d3"},
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{0, DREG, 04, "d4"},
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{0, DREG, 05, "d5"},
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{0, DREG, 06, "d6"},
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{0, DREG, 07, "d7"},
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{0, AREG, 00, "a0"},
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{0, AREG, 01, "a1"},
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{0, AREG, 02, "a2"},
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{0, AREG, 03, "a3"},
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{0, AREG, 04, "a4"},
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{0, AREG, 05, "a5"},
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{0, AREG, 06, "a6"},
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{0, AREG, 07, "a7"},
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{0, AREG, 07, "sp"},
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{0, PC, 0, "pc"},
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{0, PC, 0200, "zpc"},
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{0, CREG, 04001, "vbr"},
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{0, CREG, 0, "sfc"},
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{0, CREG, 00001, "dfc"},
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{0, CREG, 00002, "cacr"},
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{0, CREG, 04002, "caar"},
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{0, CREG, 04003, "msp"},
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{0, CREG, 04004, "isp"},
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{0, SPEC, 075, "usp"},
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{0, SPEC, 076, "ccr"},
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{0, SPEC, 077, "sr"},
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{0, ABCD, 0140400, "abcd"},
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{0, ABCD, 0100400, "sbcd"},
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{0, ADDX, 0150400, "addx"},
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{0, ADDX, 0110400, "subx"},
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{0, ADD, 0153300, "add"},
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{0, ADD, 0112700, "sub"},
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{0, AND, 0141000, "and"},
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{0, AND, 0135000, "eor"},
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{0, AND, 0100000, "or"},
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{0, BITOP, 0000, "btst"},
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{0, BITOP, 0100, "bchg"},
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{0, BITOP, 0200, "bclr"},
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{0, BITOP, 0300, "bset"},
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{0, BITFIELD, 0164300, "bftst"},
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{0, BITFIELD, 0165300, "bfchg"},
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{0, BITFIELD, 0166300, "bfclr"},
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{0, BITFIELD, 0167300, "bfset"},
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{0, BF_TO_D, 0164700, "bfextu"},
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{0, BF_TO_D, 0165700, "bfexts"},
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{0, BF_TO_D, 0166700, "bfffo"}, /* not 0164700 */
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{0, BFINS, 0167700, "bfins"},
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{0, SHIFT, 0160340, "asr"},
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{0, SHIFT, 0160740, "asl"},
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{0, SHIFT, 0161350, "lsr"},
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{0, SHIFT, 0161750, "lsl"},
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{0, SHIFT, 0162360, "roxr"},
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{0, SHIFT, 0162760, "roxl"},
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{0, SHIFT, 0163370, "ror"},
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{0, SHIFT, 0163770, "rol"},
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{0, SZ_EA, 041000|DTA|ALT, "clr"},
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{0, SZ_EA, 042000|DTA|ALT, "neg"},
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{0, SZ_EA, 040000|DTA|ALT, "negx"},
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{0, SZ_EA, 043000|DTA|ALT, "not"},
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{0, SZ_EA, 045000, "tst"},
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{0, OP_EA, 044000|DTA|ALT, "nbcd"},
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{0, OP_EA, 045300|DTA|ALT, "tas"},
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{0, OP_EA, 047200|CTR, "jsr"},
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{0, OP_EA, 047300|CTR, "jmp"},
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{0, OP_EA, 044100|CTR, "pea"},
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{0, OP_EA, 050300, "st"},
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{0, OP_EA, 050700, "sf"},
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{0, OP_EA, 051300, "shi"},
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{0, OP_EA, 051700, "sls"},
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{0, OP_EA, 052300, "scc"},
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{0, OP_EA, 052700, "scs"},
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{0, OP_EA, 053300, "sne"},
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{0, OP_EA, 053700, "seq"},
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{0, OP_EA, 054300, "svc"},
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{0, OP_EA, 054700, "svs"},
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{0, OP_EA, 055300, "spl"},
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{0, OP_EA, 055700, "smi"},
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{0, OP_EA, 056300, "sge"},
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{0, OP_EA, 056700, "slt"},
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{0, OP_EA, 057300, "sgt"},
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{0, OP_EA, 057700, "sle"},
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{0, OP_NOOP, 047160, "reset"},
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{0, OP_NOOP, 047161, "nop"},
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{0, OP_NOOP, 047163, "rte"},
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{0, OP_NOOP, 047165, "rts"},
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{0, OP_NOOP, 047166, "trapv"},
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{0, OP_NOOP, 047167, "rtr"},
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{0, OP_NOOP, 045374, "illegal"},
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{0, PACK, 0100500, "pack"},
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{0, PACK, 0100600, "unpk"},
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{0, DIVMUL, 0100, "divu"},
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{0, DIVMUL, 0101, "divs"},
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{0, DIVMUL, 0000, "mulu"},
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{0, DIVMUL, 0001, "muls"},
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{0, DIVL, 046100, "divul"},
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{0, DIVL, 046101, "divsl"},
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{0, BR, 060000, "bra"},
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{0, BR, 060400, "bsr"},
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{0, BR, 061000, "bhi"},
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{0, BR, 061400, "bls"},
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{0, BR, 062000, "bcc"},
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{0, BR, 062400, "bcs"},
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{0, BR, 063000, "bne"},
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{0, BR, 063400, "beq"},
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{0, BR, 064000, "bvc"},
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{0, BR, 064400, "bvs"},
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{0, BR, 065000, "bpl"},
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{0, BR, 065400, "bmi"},
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{0, BR, 066000, "bge"},
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{0, BR, 066400, "blt"},
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{0, BR, 067000, "bgt"},
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{0, BR, 067400, "ble"},
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{0, DBR, 050310, "dbt"},
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{0, DBR, 050710, "dbf"},
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{0, DBR, 050710, "dbra"},
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{0, DBR, 051310, "dbhi"},
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{0, DBR, 051710, "dbls"},
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{0, DBR, 052310, "dbcc"},
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{0, DBR, 052710, "dbcs"},
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{0, DBR, 053310, "dbne"},
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{0, DBR, 053710, "dbeq"},
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{0, DBR, 054310, "dbvc"},
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{0, DBR, 054710, "dbvs"},
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{0, DBR, 055310, "dbpl"},
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{0, DBR, 055710, "dbmi"},
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{0, DBR, 056310, "dbge"},
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{0, DBR, 056710, "dblt"},
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{0, DBR, 057310, "dbgt"},
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{0, DBR, 057710, "dble"},
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{0, OP_EXT, 044000, "ext"},
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{0, OP_EXT, 044400, "extb"},
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{0, OP_RANGE, 04000, "chk2"},
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{0, OP_RANGE, 0, "cmp2"},
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{0, TRAPCC, 050370, "trapt"},
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{0, TRAPCC, 050770, "trapf"},
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{0, TRAPCC, 051370, "traphi"},
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{0, TRAPCC, 051770, "trapls"},
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{0, TRAPCC, 052370, "trapcc"},
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{0, TRAPCC, 052770, "trapcs"},
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{0, TRAPCC, 053370, "trapeq"},
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{0, TRAPCC, 053770, "trapvc"},
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{0, TRAPCC, 054370, "trapvs"},
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{0, TRAPCC, 054770, "trappl"},
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{0, TRAPCC, 055370, "trapmi"},
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{0, TRAPCC, 055770, "trapge"},
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{0, TRAPCC, 056370, "traplt"},
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{0, TRAPCC, 056770, "trapgt"},
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{0, TRAPCC, 057370, "traple"},
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{0, TRAPCC, 057770, "trapne"},
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{0, CMP, 0, "cmp"},
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{0, MOVE, 0, "move"},
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{0, MOVESP, 0, "movep"},
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{0, MOVEM, 0, "movem"},
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{0, MOVESP, 1, "moves"},
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{0, MOVEC, 0, "movec"},
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{0, SWAP, 0, "swap"},
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{0, LINK, 0, "link"},
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{0, UNLK, 0, "unlk"},
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{0, TRAP, 0, "trap"},
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{0, OP_IMM, 047162, "stop"},
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{0, CHK, 0, "chk"},
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{0, RTM, 0, "rtm"},
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{0, EXG, 0, "exg"},
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{0, LEA, 0, "lea"},
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{0, OP_IMM, 047164, "rtd"},
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{0, BKPT, 0, "bkpt"},
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{0, CALLM, 0, "callm"},
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{0, CAS, 0, "cas"},
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{0, CAS2, 0, "cas2"},
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{0, CP, 00000, "c0"},
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{0, CP, 01000, "c1"},
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{0, CP, 02000, "c2"},
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{0, CP, 03000, "c3"},
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{0, CP, 04000, "c4"},
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{0, CP, 05000, "c5"},
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{0, CP, 06000, "c6"},
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{0, CP, 07000, "c7"},
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/* ???? what is this ???? */
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{0, CPGEN, 0170000, ".gen"},
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{0, CPSCC, 0170100, ".s"},
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{0, CPDBCC, 0170110, ".db"},
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{0, CPTRAPCC, 0170170, ".trap"},
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{0, CPBCC, 0170200, ".br"}, /* 'r' to distinguish from SIZE_B
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*/
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{0, CPSAVREST, 0170400, ".save"},
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{0, CPSAVREST, 0170500, ".restore"},
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/* ???? end of what is this ???? */
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/* M68030 MMU registers */
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{0, MREG, 0040000, "tc"},
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{0, MREG, 0044000, "srp"},
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{0, MREG, 0046000, "crp"},
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{0, MREG, 0060000, "mmusr"},
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{0, MREG, 0060000, "psr"},
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{0, MREG, 0004000, "tt0"},
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{0, MREG, 0006000, "tt1"},
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/* M68030 MMU instructions */
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{0, PFLUSHA, 0022000, "pflusha"},
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{0, PFLUSH, 0020000, "pflush"},
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{0, PLOAD, 0021000, "ploadr"},
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{0, PLOAD, 0020000, "ploadw"},
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{0, PTEST, 0101000, "ptestr"},
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{0, PTEST, 0100000, "ptestw"},
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{0, PMOVE, 0000000, "pmove"},
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{0, PMOVE, 0000400, "pmovefd"},
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/* floating point coprocessor ... */
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{0, FSIZE, FSIZE_S, ".s"},
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{0, FSIZE, FSIZE_X, ".x"},
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{0, FSIZE, FSIZE_P, ".p"},
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{0, FSIZE, FSIZE_D, ".d"},
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{0, FPREG, 0, "fp0"},
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{0, FPREG, 1, "fp1"},
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{0, FPREG, 2, "fp2"},
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{0, FPREG, 3, "fp3"},
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{0, FPREG, 4, "fp4"},
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{0, FPREG, 5, "fp5"},
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{0, FPREG, 6, "fp6"},
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{0, FPREG, 7, "fp7"},
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{0, FPCR, 1, "fpiar"},
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{0, FPCR, 2, "fpsr"},
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{0, FPCR, 4, "fpcr"},
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{0, FMOVE, 0, "fmove"},
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{0, FMOVECR, 0, "fmovecr"},
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{0, FMOVEM, 0, "fmovem"},
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{0, FDYADIC, 042, "fadd"},
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{0, FDYADIC, 070, "fcmp"},
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{0, FDYADIC, 040, "fdiv"},
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{0, FDYADIC, 041, "fmod"},
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{0, FDYADIC, 043, "fmul"},
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{0, FDYADIC, 045, "frem"},
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{0, FDYADIC, 046, "fscale"},
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{0, FDYADIC, 044, "fsgldiv"},
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{0, FDYADIC, 047, "fsglmul"},
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{0, FDYADIC, 050, "fsub"},
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{0, FMONADIC, 030, "fabs"},
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{0, FMONADIC, 034, "facos"},
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{0, FMONADIC, 014, "fasin"},
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{0, FMONADIC, 012, "fatan"},
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{0, FMONADIC, 015, "fatanh"},
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{0, FMONADIC, 035, "fcos"},
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{0, FMONADIC, 031, "fcosh"},
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{0, FMONADIC, 020, "fetox"},
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{0, FMONADIC, 010, "fetoxm1"},
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{0, FMONADIC, 036, "fgetexp"},
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{0, FMONADIC, 037, "fgetman"},
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{0, FMONADIC, 001, "fint"},
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{0, FMONADIC, 003, "fintrz"},
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{0, FMONADIC, 024, "flogn"},
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{0, FMONADIC, 006, "flognp1"},
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{0, FMONADIC, 025, "flog10"},
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{0, FMONADIC, 026, "flog2"},
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{0, FMONADIC, 032, "fneg"},
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{0, FMONADIC, 016, "fsin"},
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{0, FMONADIC, 002, "fsinh"},
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{0, FMONADIC, 004, "fsqrt"},
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{0, FMONADIC, 017, "ftan"},
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{0, FMONADIC, 011, "ftanh"},
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{0, FMONADIC, 022, "ftentox"},
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{0, FMONADIC, 021, "ftwotox"},
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{0, FSINCOS, 060, "fsincos"},
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{0, FBCC, 001, "fbeq"},
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{0, FBCC, 016, "fbne"},
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{0, FBCC, 022, "fbgt"},
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{0, FBCC, 035, "fbngt"},
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{0, FBCC, 023, "fbge"},
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{0, FBCC, 034, "fbnge"},
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{0, FBCC, 024, "fblt"},
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{0, FBCC, 033, "fbnlt"},
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{0, FBCC, 025, "fble"},
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{0, FBCC, 032, "fbnle"},
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{0, FBCC, 026, "fbgl"},
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{0, FBCC, 031, "fbngl"},
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{0, FBCC, 027, "fbgle"},
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{0, FBCC, 030, "fbngle"},
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{0, FBCC, 002, "fbogt"},
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{0, FBCC, 015, "fbule"},
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{0, FBCC, 003, "fboge"},
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{0, FBCC, 014, "fbult"},
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{0, FBCC, 004, "fbolt"},
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{0, FBCC, 013, "fbuge"},
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{0, FBCC, 005, "fbole"},
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{0, FBCC, 012, "fbugt"},
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{0, FBCC, 006, "fbogl"},
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{0, FBCC, 011, "fbueq"},
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{0, FBCC, 007, "fbor"},
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{0, FBCC, 010, "fbun"},
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{0, FBCC, 000, "fbf"},
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{0, FBCC, 017, "fbt"},
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{0, FBCC, 020, "fbsf"},
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{0, FBCC, 037, "fbst"},
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{0, FBCC, 021, "fbseq"},
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{0, FBCC, 036, "fbsne"},
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{0, FDBCC, 001, "fdbeq"},
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{0, FDBCC, 016, "fdbne"},
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{0, FDBCC, 022, "fdbgt"},
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{0, FDBCC, 035, "fdbngt"},
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{0, FDBCC, 023, "fdbge"},
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{0, FDBCC, 034, "fdbnge"},
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{0, FDBCC, 024, "fdblt"},
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{0, FDBCC, 033, "fdbnlt"},
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{0, FDBCC, 025, "fdble"},
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{0, FDBCC, 032, "fdbnle"},
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{0, FDBCC, 026, "fdbgl"},
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{0, FDBCC, 031, "fdbngl"},
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{0, FDBCC, 027, "fdbgle"},
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{0, FDBCC, 030, "fdbngle"},
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{0, FDBCC, 002, "fdbogt"},
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{0, FDBCC, 015, "fdbule"},
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{0, FDBCC, 003, "fdboge"},
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{0, FDBCC, 014, "fdbult"},
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{0, FDBCC, 004, "fdbolt"},
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{0, FDBCC, 013, "fdbuge"},
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{0, FDBCC, 005, "fdbole"},
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{0, FDBCC, 012, "fdbugt"},
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{0, FDBCC, 006, "fdbogl"},
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{0, FDBCC, 011, "fdbueq"},
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{0, FDBCC, 007, "fdbor"},
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{0, FDBCC, 010, "fdbun"},
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{0, FDBCC, 000, "fdbf"},
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{0, FDBCC, 017, "fdbt"},
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{0, FDBCC, 020, "fdbsf"},
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{0, FDBCC, 037, "fdbst"},
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{0, FDBCC, 021, "fdbseq"},
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{0, FDBCC, 036, "fdbsne"},
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{0, FNOP, 0, "fnop"},
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{0, FSCC, 001, "fseq"},
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{0, FSCC, 016, "fsne"},
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{0, FSCC, 022, "fsgt"},
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{0, FSCC, 035, "fsngt"},
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{0, FSCC, 023, "fsge"},
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{0, FSCC, 034, "fsnge"},
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{0, FSCC, 024, "fslt"},
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{0, FSCC, 033, "fsnlt"},
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{0, FSCC, 025, "fsle"},
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{0, FSCC, 032, "fsnle"},
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{0, FSCC, 026, "fsgl"},
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{0, FSCC, 031, "fsngl"},
|
|
{0, FSCC, 027, "fsgle"},
|
|
{0, FSCC, 030, "fsngle"},
|
|
{0, FSCC, 002, "fsogt"},
|
|
{0, FSCC, 015, "fsule"},
|
|
{0, FSCC, 003, "fsoge"},
|
|
{0, FSCC, 014, "fsult"},
|
|
{0, FSCC, 004, "fsolt"},
|
|
{0, FSCC, 013, "fsuge"},
|
|
{0, FSCC, 005, "fsole"},
|
|
{0, FSCC, 012, "fsugt"},
|
|
{0, FSCC, 006, "fsogl"},
|
|
{0, FSCC, 011, "fsueq"},
|
|
{0, FSCC, 007, "fsor"},
|
|
{0, FSCC, 010, "fsun"},
|
|
{0, FSCC, 000, "fsf"},
|
|
{0, FSCC, 017, "fst"},
|
|
{0, FSCC, 020, "fssf"},
|
|
{0, FSCC, 037, "fsst"},
|
|
{0, FSCC, 021, "fsseq"},
|
|
{0, FSCC, 036, "fssne"},
|
|
|
|
{0, FTST, 0, "ftst"},
|
|
|
|
{0, FSAVRES, MEM|ALT|0430, "fsave"},
|
|
{0, FSAVRES, MEM|0540, "frestore"},
|
|
|
|
{0, FTRAPCC, 001, "ftrapeq"},
|
|
{0, FTRAPCC, 016, "ftrapne"},
|
|
{0, FTRAPCC, 022, "ftrapgt"},
|
|
{0, FTRAPCC, 035, "ftrapngt"},
|
|
{0, FTRAPCC, 023, "ftrapge"},
|
|
{0, FTRAPCC, 034, "ftrapnge"},
|
|
{0, FTRAPCC, 024, "ftraplt"},
|
|
{0, FTRAPCC, 033, "ftrapnlt"},
|
|
{0, FTRAPCC, 025, "ftraple"},
|
|
{0, FTRAPCC, 032, "ftrapnle"},
|
|
{0, FTRAPCC, 026, "ftrapgl"},
|
|
{0, FTRAPCC, 031, "ftrapngl"},
|
|
{0, FTRAPCC, 027, "ftrapgle"},
|
|
{0, FTRAPCC, 030, "ftrapngle"},
|
|
{0, FTRAPCC, 002, "ftrapogt"},
|
|
{0, FTRAPCC, 015, "ftrapule"},
|
|
{0, FTRAPCC, 003, "ftrapoge"},
|
|
{0, FTRAPCC, 014, "ftrapult"},
|
|
{0, FTRAPCC, 004, "ftrapolt"},
|
|
{0, FTRAPCC, 013, "ftrapuge"},
|
|
{0, FTRAPCC, 005, "ftrapole"},
|
|
{0, FTRAPCC, 012, "ftrapugt"},
|
|
{0, FTRAPCC, 006, "ftrapogl"},
|
|
{0, FTRAPCC, 011, "ftrapueq"},
|
|
{0, FTRAPCC, 007, "ftrapor"},
|
|
{0, FTRAPCC, 010, "ftrapun"},
|
|
{0, FTRAPCC, 000, "ftrapf"},
|
|
{0, FTRAPCC, 017, "ftrapt"},
|
|
{0, FTRAPCC, 020, "ftrapsf"},
|
|
{0, FTRAPCC, 037, "ftrapst"},
|
|
{0, FTRAPCC, 021, "ftrapseq"},
|
|
{0, FTRAPCC, 036, "ftrapsne"},
|