666 lines
15 KiB
C
666 lines
15 KiB
C
/* $Header$ */
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/*
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* (c) copyright 1987 by the Vrije Universiteit, Amsterdam, The Netherlands.
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* See the copyright notice in the ACK home directory, in the file "Copyright".
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*/
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/*
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* Motorola 68020 syntax rules
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*/
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/* Please do not add more terminal symbols. As it is, 127 terminal symbols
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are used, and this is the limit for some "yacc" implementations,
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notably the Ultrix one.
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*/
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operation
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: { instrp = instr;
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dot_offset = 0;
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}
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instruction
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{ emit_instr();
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}
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;
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instruction
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: bcdx DREG ',' DREG
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{ T_EMIT2($1 | $2 | $4<<9,0,0,0);}
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| bcdx '-' '(' AREG ')' ',' '-' '(' AREG ')'
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{ T_EMIT2($1 | $4 | $9<<9 | 010,0,0,0);}
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| ADD sizedef ea_ea
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{ add($1, $2);}
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| AND sizenon ea_ea
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{ and($1, $2);}
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| SHIFT sizedef ea_ea
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{ shift_op($1, $2);}
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| SHIFT sizedef ea /* This syntax is also allowed */
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{ checksize($2, 2);
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T_EMIT2(($1 & 0177700) | mrg_2,0,0,0);
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ea_2(SIZE_W, MEM|ALT);
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}
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| BR expr
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{ branch($1, $2);}
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| DBR DREG ',' expr
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{ T_EMIT2($1 | $2,0,0,0);
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$4.val -= (DOTVAL+dot_offset);
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fit(fitw($4.val));
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T_EMIT2(loww($4.val), $4.typ,
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RELPC|RELO2, relonami);
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}
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| BITOP ea_ea
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{ bitop($1);}
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| BITFIELD ea off_width
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{ bitfield($1, $3);}
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| BF_TO_D ea off_width ',' DREG
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{ bitfield($1, $3 | $5<<12);}
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| BFINS DREG ',' ea off_width
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{ bitfield($1, $5 | $2<<12);}
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| DIVMUL sizedef ea ',' DREG
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{ checksize($2, 2|4);
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if ($2 == SIZE_W) {
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T_EMIT2((0140300^($1<<8))|mrg_2|$5<<9,
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0, 0, 0);
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ea_2(SIZE_W, DTA);
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}
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else { /* 32 bit dividend or product */
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T_EMIT2((046000 | ($1 & ~1)) | mrg_2,
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0, 0, 0);
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T_EMIT2(($1&1)<<11 | $5<<12 | $5,
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0, 0, 0);
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ea_2(SIZE_L, DTA);
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}
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}
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| DIVMUL sizedef ea ',' DREG ':' DREG
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{ /* 64 bit dividend or product */
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checksize($2, 4);
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T_EMIT2((046000 | ($1 & ~1)) | mrg_2, 0, 0, 0);
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T_EMIT2(($1&1)<<11 | $7<<12 | $5 | 02000 ,0,0,0);
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ea_2(SIZE_L, DTA);
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}
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| DIVL sizedef ea ',' DREG ':' DREG
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{ /* 32 bit long division with remainder */
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checksize($2, 4);
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T_EMIT2(($1 & ~1) | mrg_2, 0, 0, 0);
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T_EMIT2(($1 & 1)<<11 | $7<<12 | $5 , 0, 0, 0);
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ea_2(SIZE_L, DTA);
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}
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| LEA ea ',' AREG
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{ T_EMIT2(040700 | mrg_2 | $4<<9,0,0,0);
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ea_2(SIZE_L, CTR);
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}
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| op_ea ea
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{ if (mrg_2==074)
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serror("bad adressing category");
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T_EMIT2(($1&0177700) | mrg_2,0,0,0);
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ea_2($1&0300, $1&017);
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}
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| OP_NOOP
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{ T_EMIT2($1,0,0,0);}
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| OP_EXT SIZE DREG
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{ checksize($2, ($1 & 0400) ? 4 : (2|4));
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T_EMIT2($1 | $2+0100 | $3,0,0,0);
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}
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| OP_RANGE sizedef ea ',' reg
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{ T_EMIT2(0300 | ($2<<3) | mrg_2,0,0,0);
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T_EMIT2($1 | ($5<<12),0,0,0);
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ea_2($2, CTR);
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}
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| TRAPCC SIZE imm
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{ checksize($2, 2|4);
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T_EMIT2($1 | ($2>>6)+1,0,0,0);
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ea_2($2, 0);
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}
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| TRAPCC { T_EMIT2($1 | 4,0,0,0);}
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| PACK '-' '(' AREG ')' ',' '-' '(' AREG ')' ',' imm
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{ T_EMIT2($1 | 8 | $4 | $9<<9, 0, 0, 0);
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ea_2(SIZE_W, 0);
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}
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| PACK DREG ',' DREG ',' imm
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{ T_EMIT2($1 | $2 | $4<<9, 0, 0, 0);
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ea_2(SIZE_W, 0);
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}
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| CMP sizedef ea_ea
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{ cmp($2);}
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| CHK sizedef ea ',' DREG
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{ checksize($2, 2|4);
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T_EMIT2(040000 | mrg_2 | $5<<9 |
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($2==SIZE_W ? 0600 : 0400),
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0, 0, 0);
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ea_2($2, DTA);
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}
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| MOVE sizenon ea_ea
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{ move($2);}
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| MOVEM sizedef regs ',' notimmreg
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{ movem(0, $2, $3);}
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| MOVEM sizedef notimmreg ',' regs
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{ movem(1, $2, $5);}
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| MOVESP sizedef ea_ea
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{ if ($1 == 0) {
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/* movep */
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movep($2);
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} else if (mrg_1 <= 017) {
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T_EMIT2(007000 | $2 | mrg_2,0,0,0);
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T_EMIT2(mrg_1 << 12 | 04000,0,0,0);
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ea_2($2,ALT|MEM);
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} else if (mrg_2 <= 017) {
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T_EMIT2(007000 | $2 | mrg_1,0,0,0);
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T_EMIT2(mrg_2 << 12,0,0,0);
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ea_1($2,ALT|MEM);
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} else
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badoperand();
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}
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| MOVEC creg ',' reg
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{ T_EMIT2(047172,0,0,0);
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T_EMIT2($2 | $4<<12,0,0,0);
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}
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| MOVEC reg ',' creg
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{ T_EMIT2(047173,0,0,0);
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T_EMIT2($4 | $2<<12,0,0,0);
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}
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| EXG reg ',' reg
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{ if (($2 & 010) == 0)
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emit2(
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(0140500|$4|$2<<9)
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+
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(($4&010)<<3)
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);
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else
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emit2(
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(0140610|$2|($4&07)<<9)
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-
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(($4&010)<<3)
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);
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}
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| SWAP DREG
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{ T_EMIT2(044100 | $2,0,0,0);}
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| OP_IMM imm
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{ T_EMIT2($1, 0, 0, 0);
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ea_2(SIZE_W, 0);
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}
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| LINK sizenon AREG ',' imm
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{ link_instr($2, $3);}
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| UNLK AREG
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{ T_EMIT2(047130 | $2,0,0,0);}
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| TRAP '#' absexp
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{ fit(fit4($3));
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T_EMIT2(047100|low4($3),0,0,0);
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}
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| BKPT '#' absexp
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{ fit(($3 & ~07) == 0);
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T_EMIT2(044110 | low3($3),0,0,0);
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}
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| CALLM '#' absexp ',' ea
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{ fit(fitb($3));
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T_EMIT2(03300 | mrg_2,0,0,0);
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T_EMIT2((short) $3,0,0,0);
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ea_2(SIZE_L, CTR);
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}
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| RTM reg
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{ T_EMIT2(03300 | $2, 0, 0, 0);}
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| CAS sizedef DREG ',' DREG ',' ea
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{ T_EMIT2(04300 | (($2+0100)<<3) | mrg_2,0,0,0);
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T_EMIT2($3 | ($5<<6),0,0,0);
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ea_2($2, MEM|ALT);
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}
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| CAS2 sizedef DREG ':' DREG ',' DREG ':' DREG ','
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'(' reg ')' ':' '(' reg ')'
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{ checksize($2 , 2|4);
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T_EMIT2(04374 | (($2+0100)<<3),0,0,0);
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T_EMIT2($3 | ($7<<6) | ($12<<12),0,0,0);
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T_EMIT2($5 | ($9<<6) | ($16<<12),0,0,0);
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}
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| fp_op
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| mm_op
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;
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bcdx : ABCD
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| ADDX sizedef
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{ $$ = $1 | $2;}
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;
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creg : CREG
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| SPEC { if ($1 != 075)
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badoperand();
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$$ = 04000;
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}
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;
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off_width /* note: these should be curly brackets, but that would
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* leave us without brackets for expressions.
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*/
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: '[' abs31 ':' abs31 ']'
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{ $$ = ($2<<6) | $4;
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}
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;
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abs31 : DREG { $$ = 040 | $1;}
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| absexp { fit(fit5($1));
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$$ = low5($1);
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}
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;
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op_ea : OP_EA
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| SZ_EA sizedef
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{ $$ = $1 | $2;}
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;
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regs : rrange
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| regs '/' rrange
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{ $$ = $1 | $3;}
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;
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rrange : reg
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{ $$ = 1<<$1;}
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| reg '-' reg
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{ if ($1 > $3)
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badoperand();
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for ($$ = 0; $1 <= $3; $1++)
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$$ |= (1<<$1);
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}
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;
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ea : DREG
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{ mrg_2 = $1;}
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| AREG
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{ mrg_2 = 010 | $1;}
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| SPEC
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{ mrg_2 = $1;}
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| notimmreg
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| imm
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;
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notimmreg
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:
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{ mrg_2 = 0; ffew_2 = 0400; /* initialization */}
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notimmreg1
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;
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notimmreg1
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: '(' AREG ')'
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{ mrg_2 = 020 | $2;}
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| '(' AREG ')' '+'
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{ mrg_2 = 030 | $2;}
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| '-' '(' AREG ')'
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{ mrg_2 = 040 | $3;}
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| '(' expr ')' sizenon
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{ bd_2 = $2; ea7071($4);
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RELOMOVE(bd_rel2, relonami);
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}
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| '(' bd_areg_index ')'
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{ if ((mrg_2 & INDEX) == 0)
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ffew_2 |= 0100; /* suppress index */
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if ( !(mrg_2 & PC_MODE) &&
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(ffew_2 & 0300) == 0100 &&
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bd_2.typ==S_ABS && fitw(bd_2.val)
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)
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mrg_2 = (loww(bd_2.val)?050:020) | $2;
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else {
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mrg_2 = (mrg_2&PC_MODE)?073:(060 | $2);
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ffew_2 |= 060; /* long displacement */
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}
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}
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| '(' '[' bd_areg_index ']' index_od ')'
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{ switch(mrg_2 & INDEX) {
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case 0:
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ffew_2 |= 0163; /* suppress index */
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break;
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case DBL_INDEX:
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serror("bad indexing");
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case PRE_INDEX:
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ffew_2 |= 063; break;
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case POST_INDEX:
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ffew_2 |= 067; break;
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}
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mrg_2 = (mrg_2 & PC_MODE) ? 073 : (060 | $3);
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}
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;
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imm : '#' expr
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{ mrg_2 = 074; bd_2 = $2;
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RELOMOVE(bd_rel2, relonami);
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}
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;
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bd_areg_index
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: /* empty */
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{ $$ = 0; ffew_2 |= 0200;
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/* base-reg suppressed */
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bd_2.typ = S_ABS; bd_2.val = (valu_t)0;
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/* zero displacement */
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}
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| expr { $$ = 0; ffew_2 |= 0200;
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bd_2 = $1;
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RELOMOVE(bd_rel2, relonami);
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}
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| areg_index
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{ bd_2.typ = S_ABS; bd_2.val = (valu_t)0;
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}
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| expr ',' areg_index
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{ $$ = $3; bd_2 = $1;
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RELOMOVE(bd_rel2, relonami);
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}
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;
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areg_index
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: areg
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| index { $$ = 0;
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ffew_2 |= 0200; /* base-reg suppressed */
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mrg_2 |= PRE_INDEX;
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}
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| areg ',' index
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{ mrg_2 |= PRE_INDEX;
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}
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;
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areg : AREG
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| PC { mrg_2 |= PC_MODE;
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ffew_2 |= $1; /* base-reg suppressed for zpc */
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$$ = 0;
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}
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;
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index : reg sizedef scale
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{ checksize($2, 2|4);
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ffew_2 |= $1<<12 | ($2&0200)<<4 | $3;
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}
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;
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scale : /* empty */
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{ $$ = 0;}
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| '*' absexp
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{ $$ = checkscale($2);}
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;
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index_od: /* empty */
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{ od_2.typ = S_ABS; od_2.val = (valu_t)0;}
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| ',' index
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{ od_2.typ = S_ABS; od_2.val = (valu_t)0;
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mrg_2 |= POST_INDEX;
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}
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| ',' expr
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{ od_2 = $2;
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RELOMOVE(od_rel2, relonami);
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}
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| ',' index ',' expr
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{ od_2 = $4;
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mrg_2 |= POST_INDEX;
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RELOMOVE(od_rel2, relonami);
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}
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;
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reg : DREG
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| AREG
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{ $$ = $1 | 010;}
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;
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sizedef : /* empty */
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{ $$ = SIZE_DEF;}
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| SIZE
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;
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sizenon : /* empty */
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{ $$ = SIZE_NON;}
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| SIZE
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;
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ea_ea : ea ','
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{ mrg_1 = mrg_2;
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bd_1 = bd_2;
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od_1 = od_2;
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ffew_1 = ffew_2;
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RELOMOVE(bd_rel1, bd_rel2);
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RELOMOVE(od_rel1, od_rel2);
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}
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ea
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;
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fp_op : CP
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{ co_id = $1; }
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fp_op1
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| { co_id = DEF_FP; }
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fp_op1
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;
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fp_op1 : FMOVE fsize ea ',' FPCR
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{ check_fsize($2, FSIZE_L);
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if ((mrg_2&070) == 010 && $5 != 001)
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badoperand();
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T_EMIT2((0170000|co_id|mrg_2),0,0,0);
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T_EMIT2((0100000|($5<<10)),0,0,0);
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ea_2(SIZE_L, 0);
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}
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| FMOVE fsize FPCR ',' ea
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{ check_fsize($2, FSIZE_L);
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if ((mrg_2&070) == 010 && $3 == 001)
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badoperand();
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T_EMIT2((0170000|co_id|mrg_2),0,0,0);
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T_EMIT2((0120000|($3<<10)),0,0,0);
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ea_2(SIZE_L, ALT);
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}
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| FMOVE fsize FPREG ',' FPREG
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{ emit2(0170000|co_id);
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emit2(($3<<10)|($5<<7));
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}
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| FMOVE fsize ea ',' FPREG
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{ ch_sz_dreg($2, mrg_2&070);
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T_EMIT2((0170000|co_id|mrg_2),0,0,0);
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T_EMIT2((0040000|($2<<10)|($5<<7)),0,0,0);
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ea_2(SIZE_L, DTA);
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}
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| FMOVE fsize FPREG ',' ea
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{ ch_sz_dreg($2, mrg_2&070);
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if ($2 == FSIZE_P)
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serror("packed decimal needs k-factor");
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T_EMIT2((0170000|co_id|mrg_2),0,0,0);
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T_EMIT2((0060000|($2<<10)|($3<<7)),0,0,0);
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ea_2(SIZE_L, DTA|ALT);
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}
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| FMOVE fsize FPREG ',' ea '{' '#' absexp '}'
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{ check_fsize($2, FSIZE_P);
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fit(sfit7($8));
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T_EMIT2((0170000|co_id|mrg_2),0,0,0);
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T_EMIT2((0066000|($3<<7)|low7($8)),0,0,0);
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ea_2(SIZE_L, MEM|DTA|ALT);
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}
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| FMOVE fsize FPREG ',' ea '{' DREG '}'
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{ check_fsize($2, FSIZE_P);
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T_EMIT2((0170000|co_id|mrg_2),0,0,0);
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T_EMIT2((0076000|($3<<7)|($7<<4)),0,0,0);
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ea_2(SIZE_L, MEM|DTA|ALT);
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}
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| FMOVECR fsize '#' absexp ',' FPREG
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{ fit(fit7($4));
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check_fsize($2, FSIZE_X);
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emit2(0170000|co_id);
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emit2(056000|($6<<7)|low7($4));
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}
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| FMOVEM FSIZE fregs ',' notimmreg
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{ check_fsize($2, FSIZE_X);
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if ((mrg_2&070) == 030)
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serror("bad addressing category");
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T_EMIT2((0170000|co_id|mrg_2),0,0,0);
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T_EMIT2(0160000 |
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(((mrg_2&070)==040 || ($3&04000)) ?
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$3 :
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(010000|reverse($3,8))),
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0,0,0);
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ea_2(SIZE_L, MEM|ALT);
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}
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| FMOVEM FSIZE notimmreg ',' fregs
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{ check_fsize($2, FSIZE_X);
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if ((mrg_2&070) == 040)
|
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serror("bad addressing category");
|
|
T_EMIT2((0170000|co_id|mrg_2),0,0,0);
|
|
T_EMIT2((0150000|(($5&04000)?$5:reverse($5,8))),0,0,0);
|
|
ea_2(SIZE_L, MEM);
|
|
}
|
|
| FMOVEM SIZE fcregs ',' ea
|
|
{ checksize($2, 4);
|
|
if ((mrg_2&070) == 1 && $3!= 02000)
|
|
serror("bad addressing category");
|
|
if ((mrg_2 & 070) == 0 &&
|
|
$3 != 02000 && $3 != 04000 && $3 != 010000)
|
|
serror("bad addressing category");
|
|
T_EMIT2((0170000|co_id|mrg_2),0,0,0);
|
|
T_EMIT2((0120000|$3),0,0,0);
|
|
ea_2(SIZE_L, ALT);
|
|
}
|
|
| FMOVEM SIZE ea ',' fcregs
|
|
{ checksize($2, 4);
|
|
if ((mrg_2&070) == 1 && $5!= 02000)
|
|
serror("bad addressing category");
|
|
if ((mrg_2 & 070) == 0 &&
|
|
$5 != 02000 && $5 != 04000 && $5 != 010000)
|
|
serror("bad addressing category");
|
|
T_EMIT2((0170000|co_id|mrg_2),0,0,0);
|
|
T_EMIT2((0100000|$5),0,0,0);
|
|
ea_2(SIZE_L, 0);
|
|
}
|
|
| FDYADIC fsize ea ',' FPREG
|
|
{ T_EMIT2((0170000|co_id|mrg_2),0,0,0);
|
|
T_EMIT2((0040000|($2<<10)|($5<<7)|$1),0,0,0);
|
|
ch_sz_dreg($2, mrg_2&070);
|
|
ea_2(SIZE_L, DTA);
|
|
}
|
|
| FDYADIC fsize FPREG ',' FPREG
|
|
{ check_fsize($2, FSIZE_X);
|
|
emit2(0170000|co_id);
|
|
emit2(($3<<10)|($5<<7)|$1);
|
|
}
|
|
| FMONADIC fsize ea ',' FPREG
|
|
{ T_EMIT2((0170000|co_id|mrg_2),0,0,0);
|
|
T_EMIT2((0040000|($2<<10)|($5<<7)|$1),0,0,0);
|
|
ch_sz_dreg($2, mrg_2&070);
|
|
ea_2(SIZE_L, DTA);
|
|
}
|
|
| FMONADIC fsize FPREG ',' FPREG
|
|
{ check_fsize($2, FSIZE_X);
|
|
emit2(0170000|co_id);
|
|
emit2(($3<<10)|($5<<7)|$1);
|
|
}
|
|
| FMONADIC fsize FPREG
|
|
{ check_fsize($2, FSIZE_X);
|
|
emit2(0170000|co_id);
|
|
emit2(($3<<10)|($3<<7)|$1);
|
|
}
|
|
| FSINCOS fsize ea ',' FPREG ':' FPREG
|
|
{ T_EMIT2(0170000|co_id|mrg_2,0,0,0);
|
|
T_EMIT2(0040000|($2<<10)|($7<<7)|$1|$5,0,0,0);
|
|
ea_2(SIZE_L, DTA);
|
|
}
|
|
| FSINCOS fsize FPREG ',' FPREG ':' FPREG
|
|
{ check_fsize($2, FSIZE_X);
|
|
emit2(0170000|co_id);
|
|
emit2(($3<<10)|($7<<7)|$1|$5);
|
|
}
|
|
| FBCC expr
|
|
{ fbranch($1, $2);}
|
|
| FDBCC DREG ',' expr
|
|
{ T_EMIT2(0170110|co_id|$2,0,0,0);
|
|
T_EMIT2($1,0,0,0);
|
|
$4.val -= (DOTVAL+dot_offset);
|
|
fit(fitw($4.val));
|
|
T_EMIT2(loww($4.val), $4.typ,
|
|
RELPC|RELO2,relonami);
|
|
}
|
|
| FNOP
|
|
{ emit2(0170200|co_id);
|
|
emit2(0);
|
|
}
|
|
| FSCC ea
|
|
{ T_EMIT2(0170100|co_id|mrg_2,0,0,0);
|
|
T_EMIT2($1,0,0,0);
|
|
ea_2(SIZE_B, DTA|ALT);
|
|
}
|
|
| FTST fsize ea
|
|
{ T_EMIT2((0170000|co_id|mrg_2),0,0,0);
|
|
T_EMIT2((0040072|($2<<10)),0,0,0);
|
|
ch_sz_dreg($2, mrg_2&070);
|
|
ea_2(SIZE_L, DTA);
|
|
}
|
|
| FTST fsize FPREG
|
|
{ check_fsize($2, FSIZE_X);
|
|
emit2(0170000|co_id);
|
|
emit2(($3<<10)|072);
|
|
}
|
|
| FSAVRES ea
|
|
{ if ((mrg_2&070) == ($1&070))
|
|
badoperand();
|
|
T_EMIT2((0170000|co_id|($1&0700)|mrg_2),0,0,0);
|
|
ea_2(0, $1&07);
|
|
}
|
|
| FTRAPCC
|
|
{ emit2(0170174|co_id);
|
|
emit2($1);
|
|
}
|
|
| FTRAPCC SIZE imm
|
|
{ checksize($2, 2|4);
|
|
T_EMIT2((0170170|co_id|($2==SIZE_L?03:02)),
|
|
0,0,0);
|
|
T_EMIT2($1,0,0,0);
|
|
ea_2($2,0);
|
|
}
|
|
;
|
|
fregs : DREG
|
|
{ $$ = 04000 | $1 << 4; }
|
|
| frlist
|
|
;
|
|
frlist : frrange
|
|
| frlist '/' frrange
|
|
{ $$ = $1 | $3;}
|
|
;
|
|
frrange : FPREG
|
|
{ $$ = 1 << $1; }
|
|
| FPREG '-' FPREG
|
|
{ if ($1 > $3)
|
|
badoperand();
|
|
for ($$ = 0; $1 <= $3; $1++)
|
|
$$ |= (1 << $1);
|
|
}
|
|
;
|
|
fcregs : FPCR
|
|
{ $$ = $1 << 10; }
|
|
| fcregs '/' FPCR
|
|
{ $$ = $1 | ($3 << 10); }
|
|
;
|
|
fsize : /* empty */
|
|
{ $$ = FSIZE_X; }
|
|
| SIZE
|
|
{ if ($1 == SIZE_L)
|
|
$$ = FSIZE_L;
|
|
else if ($1 == SIZE_W)
|
|
$$ = FSIZE_W;
|
|
else $$ = FSIZE_B;
|
|
}
|
|
| FSIZE
|
|
;
|
|
mm_op : CP
|
|
{ co_id = $1; }
|
|
mm_op1
|
|
| { co_id = DEF_MM; }
|
|
mm_op1
|
|
;
|
|
mm_op1 : /* Coprocessor instructions; syntax may be changed (please).
|
|
* No coprocessor defined extension words are emitted.
|
|
*/
|
|
CPBCC cp_cond expr
|
|
{ cpbcc($1 | co_id | $2, $3);
|
|
}
|
|
| CPDBCC cp_cond DREG ',' expr
|
|
{ T_EMIT2($1 | co_id | $3,0,0,0);
|
|
$5.val -= (DOTVAL+dot_offset);
|
|
fit(fitw($5.val));
|
|
T_EMIT2(loww($5.val), $5.typ,
|
|
RELPC|RELO2, relonami);
|
|
}
|
|
| CPGEN
|
|
{ T_EMIT2($1 | co_id,0,0,0);
|
|
/* NO COMMAND WORD IS EMITTED;
|
|
* THIS INSTRUCTIONS IS (STILL) ONE BIG RIDDLE.
|
|
* NO EFFECTIVE ADDRESS IS CALCULATED (SYNTAX ?)
|
|
*/
|
|
}
|
|
| CPSAVREST ea
|
|
{ T_EMIT2($1 | co_id | mrg_2,0,0,0);
|
|
if ($1 & 0100) {
|
|
/* restore */
|
|
ea_2(SIZE_W, (mrg_2 & 070)==030 ? 0 : CTR);
|
|
}
|
|
else ea_2(SIZE_W,(mrg_2 & 070)==020 ? 0 : CTR|ALT);
|
|
}
|
|
| CPSCC cp_cond ea
|
|
{ T_EMIT2($1 | co_id | mrg_2,0,0,0);
|
|
T_EMIT2($2,0,0,0);
|
|
ea_2(SIZE_B,DTA|ALT);
|
|
}
|
|
| CPTRAPCC cp_cond SIZE imm
|
|
{ checksize($3,2|4);
|
|
T_EMIT2($1 | co_id | ($3>>6)+1,0,0,0);
|
|
T_EMIT2($2,0,0,0);
|
|
ea_2($3, 0);
|
|
}
|
|
| CPTRAPCC cp_cond
|
|
{ T_EMIT2($1 | co_id | 4,0,0,0);
|
|
T_EMIT2($2,0,0,0);
|
|
}
|
|
;
|
|
cp_cond : DOT absexp
|
|
{ fit(fit6($2));
|
|
$$ = low6($2);
|
|
}
|
|
;
|