533 lines
9.8 KiB
C
533 lines
9.8 KiB
C
/*
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* (c) copyright 1987 by the Vrije Universiteit, Amsterdam, The Netherlands.
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* See the copyright notice in the ACK home directory, in the file "Copyright".
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*/
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#define RCSID5 "$Header$"
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/*
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* INTEL 80386 special routines
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*/
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ea_1(param) {
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if (is_expr(reg_1)) {
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serror("bad operand");
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return;
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}
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if (is_reg(reg_1)) {
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switch(reg_1&07) {
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case 4:
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emit1(0300 | param | 04);
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emit1(0300 | 0100);
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default:
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emit1(0300 | param | (reg_1&07));
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}
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return;
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}
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if (rm_1 == 04) {
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/* sib field use here */
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emit1(mod_1 << 6 | param | 04);
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emit1(sib_1 | reg_1);
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if ((mod_1 == 0 && reg_1 == 5) || mod_1 == 2) {
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#ifdef RELOCATION
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RELOMOVE(relonami, rel_1);
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newrelo(exp_1.typ, RELO4);
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#endif
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emit4((long)(exp_1.val));
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}
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else if (mod_1 == 1) emit1((int)(exp_1.val));
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return;
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}
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emit1(mod_1<<6 | param | (reg_1&07));
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if ((mod_1 == 0 && reg_1 == 5) || mod_1 == 2) {
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#ifdef RELOCATION
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RELOMOVE(relonami, rel_1);
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newrelo(exp_1.typ, RELO4);
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#endif
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emit4((long)(exp_1.val));
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}
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else if (mod_1 == 1) {
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emit1((int)(exp_1.val));
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}
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}
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ea_2(param) {
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op_1 = op_2;
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RELOMOVE(rel_1, rel_2);
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ea_1(param);
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}
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int
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checkscale(val)
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valu_t val;
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{
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int v = val;
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if (v != val) v = 0;
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switch(v) {
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case 1:
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return 0;
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case 2:
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return 1 << 6;
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case 4:
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return 2 << 6;
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case 8:
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return 3 << 6;
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default:
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serror("bad scale");
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return 0;
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}
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/*NOTREACHED*/
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}
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reverse() {
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struct operand op;
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#ifdef RELOCATION
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int r = rel_1;
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rel_1 = rel_2; rel_2 = r;
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#endif
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op = op_1; op_1 = op_2; op_2 = op;
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}
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badsyntax() {
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serror("bad operands");
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}
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regsize(sz)
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int sz;
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{
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register int bit;
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bit = (sz&1) ? 0 : IS_R8;
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if ((is_reg(reg_1) && (reg_1 & IS_R8) != bit) ||
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(is_reg(reg_2) && (reg_2 & IS_R8) != bit))
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serror("register error");
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}
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indexed() {
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mod_2 = 0;
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if (sib_2 == -1)
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serror("register error");
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if (rm_2 == 0 && reg_2 == 4) {
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/* base register sp, no index register; use
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indexed mode without index register
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*/
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rm_2 = 04;
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sib_2 = 044;
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}
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if (reg_2 == 015) {
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reg_2 = 05;
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return;
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}
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if (exp_2.typ != S_ABS || fitb(exp_2.val) == 0)
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mod_2 = 02;
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else if (exp_2.val != 0 || reg_2 == 5)
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mod_2 = 01;
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}
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ebranch(opc,exp)
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register int opc;
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expr_t exp;
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{
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/* Conditional branching; Full displacements are available
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on the 80386, so the welknown trick with the reverse branch
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over a jump is not needed here.
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The only complication here is with the address size, which
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can be set with a prefix. In this case, the user gets what
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he asked for.
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*/
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register int sm;
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register long dist;
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int saving = address_long ? 4 : 2;
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dist = exp.val - (DOTVAL + 2);
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if (pass == PASS_2 && dist > 0 && !(exp.typ & S_DOT))
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dist -= DOTGAIN;
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sm = dist > 0 ? fitb(dist-saving) : fitb(dist);
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if ((exp.typ & ~S_DOT) != DOTTYP)
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sm = 0;
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if ((sm = small(sm,saving)) == 0) {
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emit1(0xF);
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emit1(opc | 0x80);
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dist -= 2;
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exp.val = dist;
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adsize_exp(exp);
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}
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else {
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emit1(opc | 0x70);
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emit1((int)dist);
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}
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}
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branch(opc,exp)
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register int opc;
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expr_t exp;
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{
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/* LOOP, JCXZ, etc. branch instructions.
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Here, the offset just must fit in a byte.
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*/
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register long dist;
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dist = exp.val - (DOTVAL + 2);
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if (pass == PASS_2 && dist > 0 && !(exp.typ & S_DOT))
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dist -= DOTGAIN;
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fit((exp.typ & ~S_DOT) == DOTTYP && fitb(dist));
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emit1(opc);
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emit1((int)dist);
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}
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pushop(opc)
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register int opc;
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{
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regsize(1);
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if (is_segreg(reg_1)) {
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/* segment register */
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if ((reg_1 & 07) <= 3)
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emit1(6 | opc | (reg_1&7)<<3);
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else {
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emit1(0xF);
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emit1(0200 | opc | ((reg_1&7)<<3));
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}
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} else if (is_reg(reg_1)) {
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/* normal register */
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emit1(0120 | opc<<3 | (reg_1&7));
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} else if (opc == 0) {
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if (is_expr(reg_1)) {
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if (exp_1.typ == S_ABS && fitb(exp_1.val)) {
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emit1(0152);
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emit1((int)(exp_1.val));
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}
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else {
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emit1(0150);
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RELOMOVE(relonami, rel_1);
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opsize_exp(exp_1, 1);
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}
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}
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else {
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emit1(0377); ea_1(6<<3);
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}
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} else {
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emit1(0217); ea_1(0<<3);
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}
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}
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opsize_exp(exp, nobyte)
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expr_t exp;
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{
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if (! nobyte) {
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#ifdef RELOCATION
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newrelo(exp.typ, RELO1);
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#endif
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emit1((int)(exp.val));
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}
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else if (operand_long) {
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#ifdef RELOCATION
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newrelo(exp.typ, RELO4);
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#endif
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emit4((long)(exp.val));
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}
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else {
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#ifdef RELOCATION
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newrelo(exp.typ, RELO2);
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#endif
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emit2((int)(exp.val));
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}
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}
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adsize_exp(exp)
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expr_t exp;
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{
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if (address_long) {
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#ifdef RELOCATION
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newrelo(exp.typ, RELO4 | RELPC);
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#endif
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emit4((long)(exp.val));
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}
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else {
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if (! fitw(exp.val)) {
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warning("offset does not fit in 2 bytes; remove prefix");
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}
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#ifdef RELOCATION
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newrelo(exp.typ, RELO2 | RELPC);
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#endif
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emit2((int)(exp.val));
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}
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}
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addop(opc)
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register int opc;
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{
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regsize(opc);
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if (is_reg(reg_2)) {
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/* Add register to register or memory */
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emit1(opc); ea_1((reg_2&7)<<3);
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} else if (is_acc(reg_1) && is_expr(reg_2)) {
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/* Add immediate to accumulator */
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emit1(opc | 4);
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RELOMOVE(relonami, rel_2);
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opsize_exp(exp_2, (opc&1));
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} else if (is_expr(reg_2)) {
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/* Add immediate to register or memory */
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if ((opc&1) == 0) {
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emit1(0200);
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} else if (exp_2.typ != S_ABS || fitb(exp_2.val) == 0) {
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emit1(0201);
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} else {
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emit1(0203); opc &= ~1;
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}
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ea_1(opc & 070);
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RELOMOVE(relonami, rel_2);
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opsize_exp(exp_2, (opc&1));
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} else if (is_reg(reg_1)) {
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/* Add register or memory to register */
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emit1(opc | 2);
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ea_2((reg_1&7)<<3);
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} else
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badsyntax();
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}
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rolop(opc)
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register int opc;
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{
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register int oreg;
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oreg = reg_2;
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reg_2 = reg_1;
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regsize(opc);
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if (oreg == (IS_R8 | 1)) {
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/* cl register */
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emit1(0322 | (opc&1)); ea_1(opc&070);
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} else if (is_expr(oreg) && exp_2.typ == S_ABS && exp_2.val == 1) {
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/* shift by 1 */
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emit1(0320 | (opc&1)); ea_1(opc&070);
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} else if (is_expr(oreg)) {
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/* shift by byte count */
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emit1(0300 | (opc & 1));
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ea_1(opc & 070);
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#ifdef RELOCATION
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RELOMOVE(relonami, rel_2);
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newrelo(exp_2.typ, RELO1);
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#endif
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emit1((int)(exp_2.val));
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}
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else
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badsyntax();
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}
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incop(opc)
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register int opc;
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{
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regsize(opc);
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if ((opc&1) && is_reg(reg_1)) {
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/* word register */
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emit1(0100 | (opc&010) | (reg_1&7));
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} else {
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emit1(0376 | (opc&1));
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ea_1(opc & 010);
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}
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}
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callop(opc)
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register int opc;
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{
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regsize(1);
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if (is_expr(reg_1)) {
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if (opc == (040+(0351<<8))) {
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RELOMOVE(relonami, rel_1);
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ebranch(0353,exp_1);
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} else {
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exp_1.val -= (DOTVAL+3);
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emit1(opc>>8);
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RELOMOVE(relonami, rel_1);
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adsize_exp(exp_1);
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}
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} else {
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emit1(0377); ea_1(opc&070);
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}
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}
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xchg(opc)
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register int opc;
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{
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regsize(opc);
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if (! is_reg(reg_1) || is_acc(reg_2)) {
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reverse();
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}
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if (opc == 1 && is_acc(reg_1) && is_reg(reg_2)) {
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emit1(0220 | (reg_2&7));
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} else if (is_reg(reg_1)) {
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emit1(0206 | opc); ea_2((reg_1&7)<<3);
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} else
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badsyntax();
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}
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test(opc)
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register int opc;
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{
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regsize(opc);
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if (is_reg(reg_2) || is_expr(reg_1))
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reverse();
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if (is_expr(reg_2)) {
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if (is_acc(reg_1)) {
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emit1(0250 | opc);
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RELOMOVE(relonami, rel_2);
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opsize_exp(exp_2, (opc&1));
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}
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else {
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emit1(0366 | opc);
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ea_1(0<<3);
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RELOMOVE(relonami, rel_2);
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opsize_exp(exp_2, (opc&1));
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}
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} else if (is_reg(reg_1)) {
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emit1(0204 | opc); ea_2((reg_1&7)<<3);
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} else
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badsyntax();
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}
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mov(opc)
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register int opc;
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{
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regsize(opc);
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if (is_segreg(reg_1)) {
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/* to segment register */
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emit1(0216); ea_2((reg_1&3)<<3);
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} else if (is_segreg(reg_2)) {
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/* from segment register */
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emit1(0214); ea_1((reg_2&3)<<3);
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} else if (is_expr(reg_2)) {
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/* from immediate */
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if (is_reg(reg_1)) {
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/* to register */
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emit1(0260 | opc<<3 | (reg_1&7));
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} else {
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/* to memory */
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emit1(0306 | opc); ea_1(0<<3);
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}
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RELOMOVE(relonami, rel_2);
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opsize_exp(exp_2, (opc&1));
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} else if (rm_1 == 05 && is_acc(reg_2)) {
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/* from accumulator to memory (displacement) */
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emit1(0242 | opc);
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RELOMOVE(relonami, rel_1);
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adsize_exp(exp_1);
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} else if (rm_2 == 05 && is_acc(reg_1)) {
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/* from memory (displacement) to accumulator */
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emit1(0240 | opc);
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RELOMOVE(relonami, rel_2);
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adsize_exp(exp_2);
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} else if (is_reg(reg_2)) {
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/* from register to memory or register */
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emit1(0210 | opc); ea_1((reg_2&7)<<3);
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} else if (is_reg(reg_1)) {
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/* from memory or register to register */
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emit1(0212 | opc); ea_2((reg_1&7)<<3);
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} else
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badsyntax();
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}
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extshft(opc, reg)
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int opc;
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{
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int oreg2 = reg_2;
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reg_2 = reg_1;
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regsize(1);
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emit1(0xF);
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if (oreg2 == (IS_R8 | 1)) {
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/* cl register */
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emit1(opc|1);
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ea_1(reg << 3);
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}
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else if (is_expr(oreg2)) {
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emit1(opc);
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ea_1(reg << 3);
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#ifdef RELOCATION
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RELOMOVE(relonami, rel_2);
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newrelo(exp_2.typ, RELO1);
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#endif
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emit1((int)(exp_2.val));
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}
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else badsyntax();
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}
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bittestop(opc)
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int opc;
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{
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regsize(1);
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emit1(0xF);
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if (is_expr(reg_2)) {
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emit1(0272);
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ea_1(opc << 3);
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#ifdef RELOCATION
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RELOMOVE(relonami, rel_2);
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newrelo(exp_2.typ, RELO1);
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#endif
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emit1((int)(exp_2.val));
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}
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else if (is_reg(reg_2)) {
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emit1(0203 | opc);
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ea_1((reg_2&7)<<3);
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}
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else badsyntax();
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}
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imul(reg)
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int reg;
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{
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/* This instruction is more elaborate on the 80386. Its most
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general form is:
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imul reg, reg_or_mem, immediate.
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This is the form processed here.
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*/
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regsize(1);
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if (is_expr(reg_1)) {
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/* To also handle
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imul reg, immediate, reg_or_mem
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*/
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reverse();
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}
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if (is_expr(reg_2)) {
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/* The immediate form; two cases: */
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if (exp_2.typ == S_ABS && fitb(exp_2.val)) {
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/* case 1: 1 byte encoding of immediate */
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emit1(0153);
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ea_1(reg << 3);
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emit1((int)(exp_2.val));
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}
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else {
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/* case 2: WORD or DWORD encoding of immediate */
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emit1(0151);
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ea_1(reg << 3);
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RELOMOVE(relonami, rel_2);
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opsize_exp(exp_2, 1);
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}
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}
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else if (is_reg(reg_1) && ((reg_1&7) == reg)) {
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/* the "reg" field and the "reg_or_mem" field are the same,
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and the 3rd operand is not an immediate ...
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*/
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if (reg == 0) {
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/* how lucky we are, the target is the ax register */
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emit1(0367);
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ea_2(06 << 3);
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}
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else {
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/* another register ... */
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emit1(0xF);
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emit1(0257);
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ea_2(reg << 3);
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}
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}
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else badsyntax();
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}
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