George Koehler c5bb3be495 Speed up register allocation by removing some register classes. ... The table for PowerPC had placed each GPR and FPR into an individual register class (like GPR3, GPR4, FPR1, FPR2), and had used these classes to coerce stack values into specific registers. But ncg does not like having many register classes. In http://tack.sourceforge.net/olddocs/ncg.pdf Hans van Staveren wrote: > Every extra property means the register set is more unorthogonal and > *cg* execution time is influenced by that, because it has to take > into account a larger set of registers that are not equivalent. So > try to keep the number of different register classes to a minimum. Recent changes to the PowerPC table have removed many coercions to specific registers. Many functions in libem switched from taking values in registers to taking them from the stack (see dc05cb2). I now remove all 64 individual register classes of GPR and FPR. In the few cases where I need a stack value in a specific register, I now do a move (as the arm and m68020 tables do). This commit speeds the compilation of some files. For my test file fconv.c, the compilation time goes from over 20 seconds to under 1 second. My fconv.c has 4 conversions from floats to integers, and the table has my experimental rules that do the conversions by allocating 4 or 5 registers.		2017-02-13 17:44:46 -05:00
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as	Add RELOLIS for PowerPC lis with ha16 or hi16.	2017-02-08 11:46:31 -05:00
libem	Add pat cms !defined($1)	2017-02-13 16:52:32 -05:00
libend	Mostly add support for the experimental and largely broken linuxppc platform.	2016-09-15 23:12:03 +02:00
mcg	Use a better NOT; and after remembering that PowerPC bit numbers are all	2017-01-07 01:03:15 +01:00
ncg	Speed up register allocation by removing some register classes.	2017-02-13 17:44:46 -05:00
top	In PowerPC top, don't delete addi r0, r0, 0	2017-01-26 12:44:32 -05:00