George Koehler f33b30ed3c Rewrite .fif8 to avoid powerpc64 fctid ... This fixes the SIGILL (illegal instruction) in startrek when firing phasers. The 32-bit processors in my PowerPC Mac and in QEMU don't have fctid, a 64-bit instruction. I got the idea from mach/proto/fp/fif8.c to extract the exponent, clear some bits to get an integer, then subtract the integer from the original value to get the fraction.		2016-10-17 00:39:59 -04:00
..
aar4.s	Rename our pseudo-opcode 'la' to 'li32'.	2016-09-18 17:03:23 -04:00
build.lua	Rewrite fef 8 in powerpc assembly.	2016-09-29 15:52:54 -04:00
cfi8.s	Archival checkin (semi-working code).	2007-11-02 18:56:58 +00:00
cfu8.s	Rename our pseudo-opcode 'la' to 'li32'.	2016-09-18 17:03:23 -04:00
cif8.s	Rename our pseudo-opcode 'la' to 'li32'.	2016-09-18 17:03:23 -04:00
csa.s	Archival checkin (semi-working code).	2007-11-02 18:56:58 +00:00
csb.s	Archival checkin (semi-working code).	2007-11-02 18:56:58 +00:00
cuf8.s	Rename our pseudo-opcode 'la' to 'li32'.	2016-09-18 17:03:23 -04:00
fd_00000000.s	Archival checkin (semi-working code).	2007-11-02 18:56:58 +00:00
fd_80000000.s	Archival checkin (semi-working code).	2007-11-02 18:56:58 +00:00
fd_FFFFFFFF.s	Archival checkin (semi-working code).	2007-11-02 18:56:58 +00:00
fef8.s	Rewrite fef 8 in powerpc assembly.	2016-09-29 15:52:54 -04:00
fif8.s	Rewrite .fif8 to avoid powerpc64 fctid	2016-10-17 00:39:59 -04:00
lar4.s	Add the missing .lar4 and .sar4 for powerpc.	2016-09-17 23:55:55 -04:00
los.s	Archival checkin (semi-working code).	2007-11-02 18:56:58 +00:00
powerpc.h	Eliminate the RELOH2 relocation, as it never worked --- the address would be	2016-09-17 12:43:15 +02:00
ret.s	Archival checkin (semi-working code).	2007-11-02 18:56:58 +00:00
sar4.s	Add the missing .lar4 and .sar4 for powerpc.	2016-09-17 23:55:55 -04:00
sts.s	Archival checkin (semi-working code).	2007-11-02 18:56:58 +00:00
tge.s	Archival checkin (semi-working code).	2007-11-02 18:56:58 +00:00